IT instruction pre-decode

Patent metadata

Field	Value
Publication number	US-9626185-B2
Application number	US-201313774093-A
Country	US
Kind code	B2
Filing date	Feb 22, 2013
Priority date	Feb 22, 2013
Publication date	Apr 18, 2017
Grant date	Apr 18, 2017

Abstract

Various techniques for processing and pre-decoding branches within an IT instruction block. Instructions are fetched and cached in an instruction cache, and pre-decode bits are generated to indicate the presence of an IT instruction and the likely boundaries of the IT instruction block. If an unconditional branch is detected within the likely boundaries of an IT instruction block, the unconditional branch is treated as if it were a conditional branch. The unconditional branch is sent to the branch direction predictor and the predictor generates a branch direction prediction for the unconditional branch.

First claim

What is claimed is:

1. An apparatus comprising:
an instruction cache configured to store instruction data and corresponding pre-decode data;
a pre-decode unit configured to:
scan instruction data stored in the instruction cache;
detect a predication instruction during said scan, wherein a predication instruction is executable to predicate a variable number of instructions; and
in response to detecting the predication instruction, generate pre-decode data to mark a given number of bytes of instruction data following the predication instruction prior to identifying boundaries between instructions within the given number of bytes of instruction data;

a decode unit coupled to the instruction cache to receive a plurality of instructions and the corresponding pre-decode data from the instruction cache; and
a branch direction predictor coupled to the decode unit and configured to predict conditional branches;
wherein in response to detecting that the pre-decode data indicates that an unconditional branch instruction is located within the marked given number of bytes, the decode unit is configured to associate a conditional branch prediction from the branch direction predictor with the unconditional branch instruction prior to determining a number of instructions to predicate based on the detected predication instruction.

2. The apparatus as recited in claim 1 , wherein the pre-decode data includes a plurality of indicators for each cache line stored in the instruction cache, wherein the pre-decode data includes an indication of a shadow of the predication instruction, wherein the shadow of the predication instruction identifies instruction data that is predicted to correspond to instructions the predicate instruction is executable to predicate.

3. The apparatus as recited in claim 1 , wherein to mark the given number of bytes, the pre-decode unit is configured to:
set a pre-decode bit for a given portion of a cache line including the predicate instruction; and
set pre-decode bits for two portions of the cache line following the given portion.

4. The apparatus as recited in claim 1 , wherein:
the instruction cache stores instruction data as cache lines;
the apparatus is configured to logically partition each cache line in the instruction cache into a plurality of equal sized portions; and
the pre-decode data includes a single indicator for each portion.

5. The apparatus as recited in claim 4 , wherein each said indicator is a single bit.

6. The apparatus as recited in claim 3 , wherein the instruction cache is configured to store instructions of varying sizes.

7. The apparatus as recited in claim 1 , wherein the predication instruction is an if-then (IT) instruction.

8. A method comprising:
storing instruction data and corresponding pre-decode data in an instruction cache;
scanning cache lines in an instruction cache to detect any predication instructions;
detecting a predication instruction during said scan, wherein a predication instruction is executable to predicate a variable number of instructions;
in response to detecting the predication instruction, generating pre-decode data to mark a given number of bytes of instruction data following the predication instruction prior to identifying boundaries between instructions within the given number of bytes of instruction data;
generating a pre-decode indicator for each portion of each cache line to indicate if the portion follows the predication instruction within a predetermined distance; and
generating a branch direction prediction for an unconditional branch instruction prior to determining a number of instructions to predicate based on the detected predication instruction, wherein the number of instructions are located within boundaries of the predication instruction, and wherein said generating is responsive to determining that the pre-decode data includes an indication that the unconditional branch instruction is located within the marked given number of bytes.

9. The method as recited in claim 8 , wherein the pre-decode data includes an indication of a shadow of the predication instruction, wherein the shadow of the predication instruction identifies instruction data that is predicted to correspond to instructions the predicate instruction is executable to predicate.

10. The method as recited in claim 8 , wherein to mark the given number of bytes, the method comprises:
setting a pre-decode bit for a given portion of a cache line including the predicate instruction; and
setting pre-decode bits for two portions of the cache line following the given portion.

11. The method as recited in claim 8 , further comprising:
storing instruction data as cache lines in the instruction cache; and
logically partitioning each cache line in the instruction cache into a plurality of equal sized portions, wherein the pre-decode data includes a single indicator for each portion.

12. The method as recited in claim 11 , wherein cache lines are loaded into the instruction cache from a lower-level cache, and wherein the lower-level cache is a level two (L2) cache.

13. The method as recited in claim 8 , wherein the predication instruction includes a condition, the method further comprising predicting a result of the condition with a branch direction predictor to generate the branch direction prediction.

14. The method as recited in claim 8 , further comprising sending the unconditional branch instruction to a decode unit from the instruction cache.

15. A method comprising:
storing instruction data and corresponding pre-decode data in an instruction cache;
scanning cache lines in an instruction cache to detect any predication instructions;
detecting a predication instruction during said scanning, wherein a predication instruction is executable to predicate a variable number of instructions;
in response to detecting the predication instruction, generating pre-decode data to mark a given number of bytes of instruction data following the predication instruction prior to identifying boundaries between instructions within the given number of bytes of instruction data;
detecting an unconditional branch instruction within the marked given number of bytes in the instruction cache prior to determining a number of instructions to predicate based on the detected predication instruction, wherein the number of instructions are located within boundaries of the predication instruction; and
generating a conditional branch prediction for the unconditional branch instruction.

16. The method as recited in claim 15 , wherein the pre-decode data includes a plurality of indicators for each cache line stored in the instruction cache, wherein the pre-decode data includes an indication of a shadow of the predication instruction, wherein the shadow of the predication instruction identifies instruction data that is predicted to correspond to instructions the predicate instruction is executable to predicate.

17. The method as recited in claim 15 , further comprising:
setting a pre-decode bit for a given portion of a cache line including the predicate instruction and setting pre-decode bits for two portions of the cache line following the given portion.

18. The method as recited in claim 15 , further comprising:
storing instruction data as cache lines in the instruction cache; and
logically partitioning each cache line in the instruction cache into a plurality of equal sized portions, wherein the pre-decode data includes a single indicator for each portion.

19. The method as recited in claim 15 , whe

Assignees

• Apple Inc

Inventors

• Sundar Shyam
• Kountanis Ian D
• Blasco-Allue Conrado
• Williams Iii Gerard R
• Lien Wei-Han
• Gunna Ramesh B

Classifications

• G06F9/3844

  using dynamic branch prediction, e.g. using branch history tables · CPC title

• G06F9/382

  Pipelined decoding, e.g. using predecoding · CPC title

• G06F9/30054 Primary

  Unconditional branch instructions · CPC title

• G06F9/3842

  Speculative instruction execution · CPC title

• G06F9/30181

  Instruction operation extension or modification · CPC title