System and method for memory command queue management and configurable memory status checking

Patent metadata

Field	Value
Publication number	US-9626106-B2
Application number	US-201514595878-A
Country	US
Kind code	B2
Filing date	Jan 13, 2015
Priority date	Jan 13, 2015
Publication date	Apr 18, 2017
Grant date	Apr 18, 2017

Abstract

Systems, apparatuses, and methods for command queue management and configurable memory status in a memory. A memory may include a controller and one or more memory integrated circuit chips, which each include memory arrays. The controller may send commands, such as read or write commands, to the one or more memory integrated circuit chips. The memory integrated circuit chips may maintain a command queue of the commands sent from the controller, thereby relieving the controller from such responsibility. Further, the memory integrated circuit chips may send an indication of an error in executing the commands, thereby relieving the controller from constant polling of the memory integrated circuit chips as to status.

First claim

What is claimed is:

1. An integrated circuit chip comprising:
a memory;
command receipt circuitry configured to receive commands from a controller of a memory system;
command queue circuitry configured to rearrange the commands in a list of the commands in response to suspending execution of one of the commands in order for the list to be indicative of a rearranged order of execution of the commands; and
poll response circuitry configured to send part or all of the list of commands in response to receipt of a poll command from the controller.

2. The integrated circuit chip of claim 1 , further comprising command status circuitry configured to store a status associated with one or more commands in the list of commands.

3. The integrated circuit chip of claim 2 , wherein the command status circuitry is configured to store the status of each of the commands in the list of commands; and
wherein the poll response circuitry is further configured to send the status of each of the commands in the list of commands in response to receipt of the poll command from the controller.

4. An integrated circuit chip:
a memory;
command receipt circuitry configured to receive commands from a controller of a memory system;
command queue circuitry configured to maintain a list of the commands;
command pass indication circuitry configured to store a pass or fail indication of each of the commands in the list of commands; and
poll response circuitry configured to send the pass or fail indication of each of the commands in the list of commands in response to receipt of a poll command from the controller.

5. An integrated circuit chip:
a memory;
command receipt circuitry configured to receive commands from a controller of a memory system;
command queue circuitry configured to store a predetermined number of the commands sent from the controller, wherein the predetermined number is determined based on how many commands may be completed during a longest bus transaction with the controller of the memory system; and
poll response circuitry configured to send, in response to receipt of a poll command from the controller, part or all of the commands maintained by the command queue circuitry.

6. The integrated circuit chip of claim 5 , wherein the commands maintained by the command queue circuitry are for execution on a first die in the memory system;
wherein the longest bus transaction comprises a longest time in which the controller communicates with another die in the memory system.

7. A controller for a memory system comprising:
communication circuitry configured to communicate with one or more memory integrated circuit chips;
command generation circuitry configured to generate and send, via the communication circuitry, one or more commands to a memory integrated circuit chip; and
error determination circuitry configured to receive, via the communication circuitry, a communication indicative of an error and to determine, based on the communication, whether an error has occurred in execution of any of the one or more commands,
wherein the communication is not in response to polling by the controller of the memory integrated circuit chip and comprises an indication whether at least a part of the memory integrated circuit chip is ready to accept an additional command.

8. The memory system controller of claim 7 , wherein the error determination circuitry is configured to determine, based on the communication, whether the error has occurred by:
determining whether the communication has been received for more than a predetermined period; and
in response to determining that the communication has been received for more than the predetermined period, determining that the error has occurred.

9. The memory system controller of claim 7 , further comprising interrupt circuitry configured to, responsive to receipt of the communication, interrupt processing of the controller.

10. The memory system controller of claim 7 , further comprising poll circuitry configured to, in response to the error determination circuitry determining the error, poll the memory integrated circuit chip regarding the error.

11. The memory system controller of claim 10 , further comprising error identification circuitry configured to, in response to the poll circuitry polling the memory integrated circuit chip regarding the error, receive an identification of the command that resulted in the error.

12. The memory system controller of claim 11 , wherein the error identification circuitry is configured to receive the identification of the command that resulted in the error by:
receiving a list of commands in the queue of the memory integrated circuit chip, and a pass or failure indication for each of the commands in the list.

13. The memory system controller of claim 10 , further comprising command queue circuitry configured to, in response to the poll circuitry polling the memory integrated circuit chip regarding the error, receive a list of commands in the queue of the memory integrated circuit chip.

14. An integrated circuit chip comprising:
a memory;
command receipt circuitry configured to receive a command from a controller of a memory system;
execution circuitry configured to execute the command received via the command receipt module;
error determination circuitry configured to determine an error in execution of the command; and
a communication generator configured to, in response to the error determination circuitry determining an error in execution of the command, generate and send a communication indicative to the controller that the error has occurred, the communication indicative of whether at least a part of the memory integrated circuit chip is ready to accept an additional command.

15. The integrated circuit chip of claim 14 , further comprising at least one line configured to send the communication to indicate readiness to accept the additional command; and
wherein the communication, when sent on the at least one line for more than a predetermined time period, is indicative to the controller than the error has occurred.

16. The integrated circuit chip of claim 15 , wherein the communication generator is configured to, in response to the error determination circuitry determining the error, maintain sending the communication on the at least one line regardless of readiness to accept the additional command.

17. The integrated circuit chip of claim 14 , further comprising at least one communication line dedicated to transmitting the communication.

18. The integrated circuit chip of claim 14 , further comprising a plurality of data lines; and
wherein the communication generator is configured to send the communication indicative to the controller that the error has occurred on one or more of the plurality of data lines.

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Llc

Inventors

• Hsu Jonathan
• Tuers Daniel
• Kuo Tien-Chien

Classifications

• G06F3/0629

  Configuration or reconfiguration of storage systems · CPC title

• G06F11/0751

  Error or fault detection not based on redundancy (power supply failures G06F1/30; network fault management H04L41/06) · CPC title

• G06F11/073 Primary

  in a memory management context, e.g. virtual memory or cache management (memory management G06F12/00; testing of static memory units G11C29/00) · CPC title

• G06F11/079

  Root cause analysis, i.e. error or fault diagnosis (in a hardware test environment G06F11/22; in a software test environment G06F11/36) · CPC title

• G06F3/061

  Improving I/O performance · CPC title