Technologies for managing power during an activation cycle

Patent metadata

Field	Value
Publication number	US-9625984-B2
Application number	US-201514671750-A
Country	US
Kind code	B2
Filing date	Mar 27, 2015
Priority date	Mar 27, 2015
Publication date	Apr 18, 2017
Grant date	Apr 18, 2017

Abstract

Technologies of managing power during an activation cycle of a processor core or other compute domain include determining new operation limits for active processor cores or other compute domains during an activation cycle of a hibernating processor core or other hibernating compute domain to reduce the likelihood of a power surge during the activation of the hibernating processor core or other compute domain. The active processor cores or other compute domain are monitored until their operating points are at or below the new operating limits. Thereafter, the hibernating processor core or other hibernating compute domain is activated.

First claim

The invention claimed is:

1. A computing device for managing power during a processor core activation cycle, the computing device comprising:
a processor control module to (i) determine a number of active processor cores of a processor of the computing device and (ii) receive an activation request for at least one hibernating processor core of the processor of the computing device, wherein the activation request includes a command that the at least one hibernating processor core become active; and
a power management module to (i) determine a new operating limit for each active processor core based on the number of active processor cores and the number of hibernating processor cores identified by the activation request, (ii) set an operating limit of each active processor core to the new operating limit, and (iii) cause, in response to the activation request, activation of the at least one hibernating processor core subsequent to setting the operating limit of each active processor core.

2. The computing device of claim 1 , wherein the power management module is further to determine an operating point of each active processor core.

3. The computing device of claim 2 , wherein the power management module is further to determine whether the operating point of each active processor core is at, or below, the new operating limit.

4. The computing device of claim 1 , wherein the at least one hibernating processor core is a processor core in a low power state.

5. The computing device of claim 1 , wherein to determine the new operating limit for each active processor core comprises to determine a voltage operating limit for each active processor core based on the number of active processor cores and the activation request.

6. The computing device of claim 1 , wherein to determine the new operating limit for each active processor core comprises to determine a voltage operating limit and a frequency operating limit for each active processor core based on the number of active processor cores and the activation request.

7. A method of managing power during a processor core activation cycle, the method comprising:
determining, by a computing device, a number of active processor cores of a processor of the computing device;
receiving an activation request for at least one hibernating processor core of the processor of the computing device, wherein the activation request includes a command that the at least one hibernating processor core become active;
determining, by the computing device, a new operating limit for each active processor core based on the number of active processor cores and the number of hibernating processor cores identified by the activation request;
setting, by the computing device, an operating limit of each active processor core to the new operating limit; and
activating, by the computing device and in response to the activation request, the at least one hibernating processor core subsequent to setting the operating limit of each active processor core.

8. The method of claim 7 , further comprising determining, by the computing device, an operating point of each active processor core.

9. The method of claim 8 , further comprising determining, by the computing device, whether the operating point of each active processor core is at, or below, the new operating limit.

10. The method of claim 7 , wherein determining the new operating limit for each active processor core comprises determining, by the computing device, a voltage operating limit for the each active processor core based on the number of active processor cores and the activation request.

11. The method of claim 7 , wherein determining the new operating limit for each active processor core comprises determining, by the computing device, a voltage operating limit and a frequency operating limit for each active processor core based on the number of active processor cores and the activation request.

12. One or more non-transitory, computer-readable storage media comprising a plurality of instructions that in response to being executed cause a computing device to:
determine a number of active processor cores of a processor of the computing device;
receive an activation request for at least one hibernating processor core of the processor of the computing device, wherein the activation request includes a command that the at least one hibernating processor core become active;
determine a new operating limit for each active processor core based on the number of active processor cores and the number of hibernating processor cores identified by the activation request;
set an operating limit of each active processor core to the new operating limit; and
activate, in response to the activation request, the at least one hibernating processor core subsequent to setting the operating limit of each active processor core.

13. The one or more non-transitory, computer-readable storage media of claim 12 , further comprising a plurality of instructions that in response to being executed cause the computing device to determine an operating point of each active processor core.

14. The one or more non-transitory, computer-readable storage media of claim 13 , further comprising a plurality of instructions that in response to being executed cause the computing device to determine whether the operating point of each active processor core is at, or below, the new operating limit.

15. The one or more non-transitory, computer-readable storage media of claim 12 , wherein to determine the number of hibernating processor cores in the processor comprises to determine which processor cores are in a low power state.

16. The one or more non-transitory, computer-readable storage media of claim 12 , wherein to determine the new operating limit for each active processor core comprises to determine a voltage operating limit for the each active processor core based on the number of active processor cores and the activation request.

17. The one or more non-transitory, computer-readable storage media of claim 12 , wherein to determine the new operating limit for each active processor core comprises to determine a voltage operating limit and a frequency operating limit for each active processor core based on the number of active processor cores and the activation request.

18. A power management system for managing power of a plurality of variable power devices during an activation cycle of another variable power device, the power management system comprising:
a power management circuit to (i) receive an activation request for a hibernating variable power device of the plurality of variable power devices, (ii) determine a number of active variable power devices of the plurality of variable power devices, (iii) determine a new operating limit for each active variable power device based on the total number of active variable power devices and the hibernating variable power device, (iv) set an operating limit of each active variable power device to the corresponding new operating limit, and (v) activate the hibernating variable power device, in response to receiving the activation request, and subsequent to setting the operating limit of each active variable power device.

19. The power management system of claim 18 , wherein to determine the new operating limit of each active variable power device comprises to determine operational requirements of each active variable power device.

20. The power management system of claim 18 , wherein to determine the new operating limit comprises to
(ii) determine a st

Assignees

• Intel Corp

Inventors

• Ramachandran Aswin
• Raman Arvind

Classifications

• G06F11/0724

  in a multiprocessor or a multi-core unit (multiprocessors per se G06F15/80) · CPC title

• G06F1/3203

  Power management, i.e. event-based initiation of a power-saving mode · CPC title

• G06F1/3228

  Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands · CPC title

• G06F1/324

  by lowering clock frequency · CPC title

• G06F1/3287 Primary

  by switching off individual functional units in the computer system · CPC title