System and method for identifying operating temperatures and modifying of integrated circuits

Patent metadata

Field	Value
Publication number	US-9625325-B2
Application number	US-201514624907-A
Country	US
Kind code	B2
Filing date	Feb 18, 2015
Priority date	Feb 18, 2015
Publication date	Apr 18, 2017
Grant date	Apr 18, 2017

Abstract

Aspects of the present disclosure include a computer-implemented method for identifying an operating temperature of an integrated circuit (IC), the method including using a computing device for: applying a test voltage to a test circuit embedded within the IC, the test circuit including a phase shift memory (PSM) element therein, wherein the PSM element crystallizes at a crystallization temperature from an amorphous phase having a first electrical resistance into a crystalline phase having a second electrical resistance, the second electrical resistance being less than the first electrical resistance; and identifying the IC as having operated above the crystallization temperature in response to a resistance of the test circuit at the test voltage being outside of the target operating range.

First claim

What is claimed is:

1. A computer-implemented method for identifying an operating temperature of an integrated circuit (IC), the method comprising using a computing device to perform actions including:
applying a test voltage to a plurality of test circuits embedded within the IC at respective test sites, each of the plurality of test circuits including a phase shift memory (PSM) element therein, wherein each PSM element crystallizes at a crystallization temperature from an amorphous phase having a first electrical resistance into a crystalline phase having a second electrical resistance, the second electrical resistance being less than the first electrical resistance;
determining whether a resistance of each test circuit of the plurality of test circuits at the test voltage is outside of a respective target operating range; and
identifying a respective one of the plurality of test circuits as having operated above the crystallization temperature in response to the resistance of the respective test circuit being outside of the respective target operating range.

2. The method of claim 1 , wherein each PSM element includes germanium antimony (GeSb).

3. The method of claim 2 , wherein each PSM element further includes one of nitrogen (N) or silicon (Si).

4. The method of claim 1 , further comprising selecting a material composition of each PSM element before the applying of the test voltage, wherein the material for each PSM element defines the target operating range.

5. The method of claim 1 , wherein each PSM element in the crystalline phase remains crystallized below the crystallization temperature.

6. The method of claim 1 , further comprising deactivating at least part of the IC in response to one of the plurality of test circuits having operated above the crystallization temperature.

7. The method of claim 1 , further comprising calculating a temperature gradient of the IC based on the determining and the identifying of the plurality of test circuits.

8. The method of claim 7 , further comprising identifying at least one hot spot of the IC from the calculated temperature gradient, the at least one hot spot including a plurality of adjacent PSM elements identified as having operated above the crystallization temperature.

9. The method of claim 1 , wherein the crystallization temperature of each PSM element is approximately 270° C.

10. The method of claim 1 , further comprising, before applying the test voltage, doping each PSM element to define the crystallization temperature of each PSM element.

11. The method of claim 1 , further comprising deactivating at least part of the IC in response to one of the plurality of test circuits having operated above the crystallization temperature.

12. A system for identifying an operating temperature of an integrated circuit (IC), the system comprising:
a plurality of test circuits embedded within the IC at respective test sites, each of the plurality of test circuits including a phase shift memory (PSM) element therein, wherein each the PSM element crystallizes at a crystallization temperature from an amorphous phase having a first electrical resistance into a crystalline phase having a second electrical resistance, the second electrical resistance being less than the first electrical resistance; and
a controller electrically connected to the plurality of test circuits and configured to perform actions including:
determining a resistance of each test circuit of the plurality of test circuits;
comparing the resistance of each test circuit of the plurality of test circuits with a respective target operating range, and
identifying a respective one of the plurality of test circuits as having operated above the crystallization temperature in response to the resistance of one of the plurality of test circuits being outside of the respective target operating range.

13. The system of claim 12 , wherein each PSM element includes germanium antimony (GeSb).

14. The system of claim 13 , wherein each PSM element further includes one of nitrogen (N) or silicon (Si).

15. The system of claim 12 , wherein each PSM element in the crystalline phase remains crystallized below the crystallization temperature.

16. The system of claim 12 , wherein the controller is further configured for calculating a temperature gradient of the IC based on the determining and the identifying of the plurality of test circuits.

17. The system of claim 12 , wherein the controller comprises one of a multimeter or a clock generator.

18. The system of claim 12 , wherein the controller is further configured for deactivating at least part of the IC in response to one of the plurality of test circuits having operated above the crystallization temperature.

19. The system of claim 16 , wherein the controller is further configured for identifying at least one hot spot of the IC from the calculated temperature gradient, the at least one hot spot including a plurality of adjacent PSM elements identified as having operated above the crystallization temperature.

20. The system of claim 19 , wherein the controller is further configured for generating a graphical display of locations where the IC operated above the crystallization temperature, based on the calculated temperature gradient.

Assignees

• Globalfoundries Inc

Inventors

• Bickford Jeanne P
• Habib Nazmul
• Li Baozhen
• Wilder Tad J

Classifications

• H10W40/00

  Arrangements for thermal protection or thermal control (integrated devices comprising arrangements for thermal protection H10D89/60) · CPC title

• G01R31/00

  Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere ({measuring superconductive properties G01R33/1238;} testing line transmission systems H04B3/46; testing or measuring semiconductors or solid state devices during manufacture {H10P74/00}) · CPC title

• G01N27/64

  using wave or particle radiation to ionise a gas, e.g. in an ionisation chamber · CPC title

• G01N17/00

  Investigating resistance of materials to the weather, to corrosion, or to light · CPC title

• G01K7/16 Primary

  using resistive elements · CPC title