WLED driver and drive control method

Patent metadata

Field	Value
Publication number	US-9622305-B2
Application number	US-201615147575-A
Country	US
Kind code	B2
Filing date	May 5, 2016
Priority date	Nov 21, 2014
Publication date	Apr 11, 2017
Grant date	Apr 11, 2017

Abstract

A WLED driver and a drive control method. The WLED driver includes 2N 2 switches, and each CS module includes 2N switches, where one end of each of N switches in the 2N switches is connected to an output end of an error amplifier, another end of each of the N switches is connected to a gate of each of N NMOS transistors, one end of each of remaining N switches is connected to a negative input end of the error amplifier, and another end of each of the remaining N switches is connected to a positive input end of each of N feedback resistors. After a control circuit generates a clock control signal group Φ group . the control circuit controls switching actions of the 2N 2 switches on a time-division basis according to the clock control signal group Φ group .

First claim

What is claimed is:

1. A White Light Emitting Diode (WLED) driver, comprising:
N channels, wherein N is a positive integer that is greater than 1, and each channel comprises a current sink (CS) module configured to drive a WLED string, wherein each CS module comprises an error amplifier (EA), an n-type metal-oxide-semiconductor (NMOS) transistor, and a feedback resistor;
at least 2N 2 switches, wherein each CS module comprises 2N switches, the 2N 2 switches constitute a switch matrix S G =S g (i, j) and a switch matrix S FB =S fb (i, j), and wherein S g (i, j) is a switch between an output end of an EA in an i th CS module and a gate of an NMOS transistor in a j th CS module, S fb (i, j) is a switch between a negative input end of the EA in the i th CS module and a positive input end of a feedback resistor in the j th CS module, and both i and j are positive integers that are less than or equal to N;
a boost converter configured to regulate an output voltage of the WLED driver according to a maximum quantity of WLEDs in a WLED string corresponding to any channel;
wherein one end of each of N switches in the 2N switches comprised in the CS module is connected to an output end of the error amplifier, another end of each of the N switches is connected to a gate of each of N NMOS transistors, one end of each of remaining N switches is connected to a negative input end of the error amplifier, another end of each of the remaining N switches is connected to a positive input end of each of N feedback resistors, and the CS module is configured to determine an intensity of a current flowing through the WLED string corresponding to the channel; and
a control circuit configured to generate a clock signal group Φ group and control switching actions of the 2N 2 switches on a time-division basis according to the clock control signal group Φ group , so that in a clock period T, an input offset voltage of the error amplifier is evenly applied on each channel in sequence on a time-division basis, wherein the clock signal group Φ group =(Φ 1 , Φ 2 , . . . , Φ N ), the clock control signal group Φ group comprises m N clock signals Φ, the N clock signals Φ are non-overlapping N-phase clock signals Φ of a same source, a clock signal Φ i+j has a delay of j×T/N in comparison with Φ i , and T is a clock period of each phase clock.

2. The WLED driver according to claim 1 , wherein the control circuit is configured to:
control, according to the clock signal Φ i , turn-on of switches in [S g 1 i , S g 2 ( i+ 1), . . . , S g (n−i+1)n, S g (n−i+2)1, . . . , S g n(i−1)] in the switch matrix S G , and turn-off of other switches in the switch matrix SG in the switch matrix S G ; and
control according to the clock signal Φ i turn-on of switches [S fb 1 i , S fb 2 ( i+ 1), . . . , S fb (n−i+1)n, S fb (n−i+2)1, . . . , S fb n(i−1) ] in the switch matrix S FB , and turn-off of other switches in the switch matrix SG in the switch matrix S FB .

3. A drive control method for use with a White Light Emitting Diode (WLED) driver, wherein the WLED driver comprises N channels, wherein N is a positive integer that is greater than 1, and each channel comprises a current sink (CS) module configured to drive a WLED string, wherein each CS module comprises an error amplifier (EA), an n-type metal-oxide-semiconductor (NMOS) transistor, a feedback resistor and 2N switches, and the WLED driver further comprises a total of 2N 2 switches, wherein one end of each of N switches in the 2N switches comprised in the CS module is connected to an output end of the EA, another end of each of the N switches is connected to a gate of each of N NMOS transistors, one end of each of remaining N switches is connected to a negative input end of the EA, another end of each of the remaining N switches is connected to a positive input end of each of N feedback resistors, and the 2N 2 switches constitute a switch matrix S G =S g (i, j) and a switch matrix S FB = S fb (i, j), wherein S g (i, j) is a switch between an output end of an error amplifier in an i th CS module and a gate of an NMOS transistor in a j th CS module, S fb (i, j) is a switch between a negative input end of the error amplifier in the i th CS module and a positive input end of a feedback resistor in the j th CS module, and both i and j are positive integers that are less than or equal to N, the method comprising:
generating a clock control signal Φ group , wherein the clock control signal group Φ group =(Φ 1 , Φ 2 , . . . , Φ N ) and comprises N clock signals Φ, the N clock signals Φ are non-overlapping N-phase clock signals Φ of a same source, a clock signal Φ i+j has a delay of j×T/N in comparison with Φ i , and T is a clock period of each phase clock; and
controlling switching actions of the 2N 2 switches on a time-division basis according to the clock control signal group Φ group , so that in a clock period T, an input offset voltage of the error amplifier is evenly applied on each channel in sequence on a time-division basis.

4. The method according to claim 3 , wherein controlling switching actions of the 2N 2 switches on a time-division basis according to the clock control signal group Φ group comprises:
controlling, according to the clock signal Φ i , turn-on of switches in [S g 1 i , S g 2 ( i+ 1), . . . , S g (n−i+1)n, S g (n−i+2)1, . . . , S g n(i−1)] in the switch matrix S G , and turn-off of other switches in the switch matrix SG in the switch matrix S G ; and controlling turn-on of switches [S fb 1 i , S fb 2 ( i+ 1), . . . , S fb (n−i+1)n, S fb (n−i+2)1, . . . , S fb n(i−1)] in the switch matrix S FB , and turn-off of other switches in the switch matrix SG in the switch matrix S FB .

Assignees

• Huawei Tech Co Ltd

Inventors

• Huang Dongqi
• Yu Xiao
• Li Hui

Classifications

• H05B45/35

  Balancing circuits · CPC title

• H05B45/46

  having LEDs disposed in parallel lines · CPC title

• H05B33/0827

  Electricity · mapped topic

• H05B33/0815 Primary

  Electricity · mapped topic

• Y02B20/42

  Cross-Sectional Technologies · mapped topic