Scrambling sequence generation in a communication system

Patent metadata

Field	Value
Publication number	US-9622246-B2
Application number	US-201414500150-A
Country	US
Kind code	B2
Filing date	Sep 29, 2014
Priority date	Oct 4, 2007
Publication date	Apr 11, 2017
Grant date	Apr 11, 2017

Abstract

Techniques for performing scrambling and descrambling in a communication system are described. In an aspect, different scrambling sequences for different channels and signals may be generated based on different cyclic shifts of a base scrambling sequence, which may be a maximal-length sequence. A scrambling sequence for a given channel may be generated by (i) determining a sequence selector value based on a channel type value and at least one parameter value for the channel and (ii) cyclically shifting the base scrambling sequence based on the sequence selector value. In another aspect, a reference signal sent on variable system bandwidth may be generated with two scrambling sequences, which may be different cyclic shifts of a base scrambling sequence. Scrambling/descrambling for positive and negative frequencies for the reference signal may be performed with the first and second scrambling sequences, respectively.

First claim

What is claimed is:

1. A method for communication, performed by at least one processor, comprising:
mapping a start of a first scrambling sequence to a center of a system bandwidth and traversing outwardly in a positive frequency direction;
mapping a start of a second scrambling sequence to the center of the system bandwidth and traversing outwardly in a negative frequency direction;
performing scrambling or descrambling for positive frequencies for a reference signal with the first scrambling sequence; and
performing scrambling or descrambling for negative frequencies for the reference signal with the second scrambling sequence.

2. The method of claim 1 , further comprising:
generating the first scrambling sequence based on a first cyclic shift of a base scrambling sequence; and
generating the second scrambling sequence based on a second cyclic shift of the base scrambling sequence.

3. The method of claim 1 , further comprising:
generating first M scrambling bits of the first scrambling sequence with at least one scrambling sequence generator, where M is determined based on the system bandwidth; and
generating first M scrambling bits of the second scrambling sequence with the at least one scrambling sequence generator.

4. The method of claim 1 , further comprising:
determining a first sequence selector value comprising a first value for a frequency polarity parameter;
determining a second sequence selector value comprising a second value for the frequency polarity parameter;
cyclically shifting a base scrambling sequence based on the first sequence selector value to obtain the first scrambling sequence; and
cyclically shifting the base scrambling sequence based on the second sequence selector value to obtain the second scrambling sequence.

5. An apparatus for communication, comprising:
at least one processor configured to:
map a start of a first scrambling sequence to a center of a system bandwidth and traverse outwardly in a positive frequency direction;
map a start of a second scrambling sequence to the center of the system bandwidth and traverse outwardly in a negative frequency direction;
perform scrambling or descrambling for positive frequencies for a reference signal with the first scrambling sequence; and
perform scrambling or descrambling for negative frequencies for the reference signal with the second scrambling sequence.

6. The apparatus of claim 5 , wherein the at least one processor is further configured to generate the first scrambling sequence based on a first cyclic shift of a base scrambling sequence, and to generate the second scrambling sequence based on a second cyclic shift of the base scrambling sequence.

7. The apparatus of claim 5 , wherein the at least one processor is further configured to generate first M scrambling bits of the first scrambling sequence with at least one scrambling sequence generator, where M is determined based on the system bandwidth, and to generate first M scrambling bits of the second scrambling sequence with the at least one scrambling sequence generator.

8. The apparatus of claim 5 , wherein the at least one processor is further configured to determine a first sequence selector value comprising a first value for a frequency polarity parameter, to determine a second sequence selector value comprising a second value for the frequency polarity parameter, to cyclically shift a base scrambling sequence based on the first sequence selector value to obtain the first scrambling sequence, and to cyclically shift the base scrambling sequence based on the second sequence selector value to obtain the second scrambling sequence.

9. A non-transitory computer-readable medium having computer executable code stored thereon, the computer executable code comprising:
code for mapping a start of a first scrambling sequence to a center of a system bandwidth and traversing outwardly in a positive frequency direction; and
code for mapping a start of a second scrambling sequence to the center of the system bandwidth and traversing outwardly in a negative frequency direction;
code for performing scrambling or descrambling for positive frequencies for a reference signal with the first scrambling sequence; and
code for performing scrambling or descrambling for negative frequencies for the reference signal with the second scrambling sequence.

10. The non-transitory computer-readable medium of claim 9 , further comprising:
code for generating the first scrambling sequence based on a first cyclic shift of a base scrambling sequence; and
code for generating the second scrambling sequence based on a second cyclic shift of the base scrambling sequence.

11. The non-transitory computer-readable medium of claim 9 , further comprising:
code for generating first M scrambling bits of the first scrambling sequence with at least one scrambling sequence generator, where M is determined based on the system bandwidth; and
code for generating first M scrambling bits of the second scrambling sequence with the at least one scrambling sequence generator.

12. The non-transitory computer-readable medium of claim 9 , further comprising:
code for determining a first sequence selector value comprising a first value for a frequency polarity parameter;
code for determining a second sequence selector value comprising a second value for the frequency polarity parameter;
code for cyclically shifting a base scrambling sequence based on the first sequence selector value to obtain the first scrambling sequence; and
code for cyclically shifting the base scrambling sequence based on the second sequence selector value to obtain the second scrambling sequence.

Assignees

• Qualcomm Inc

Inventors

• Gaal Peter
• Montojo Juan

Classifications

• H04L25/03866 Primary

  using scrambling · CPC title

• G06F7/584 Primary

  using finite field arithmetic, e.g. using a linear feedback shift register · CPC title

• H04L5/0016

  Time-frequency-code · CPC title

• H04L5/0048

  Allocation of pilot signals, i.e. of signals known to the receiver (allocation of control signalling H04L5/0053; use of control signalling H04L5/0091) · CPC title

• H04W72/0466 Primary

  the resource being a scrambling code · CPC title