Dynamic load balancing for video decoding using multiple processors

Patent metadata

Field	Value
Publication number	US-9621908-B2
Application number	US-201213602193-A
Country	US
Kind code	B2
Filing date	Sep 2, 2012
Priority date	Sep 6, 2011
Publication date	Apr 11, 2017
Grant date	Apr 11, 2017

Abstract

A method and computer readable medium storing a corresponding computer program for decoding a video bitstream based on processors using dynamic load balancing are disclosed. In one embodiment of the present invention, the method configures multiple processors to perform the multiple processing modules including a prediction module by mapping the multiple processing modules to the multiple processors. One or more buffer queues are used among said multiple processing modules and the mapping the prediction module to the multiple processors is based on the level of the buffer queue. The multiple processors may correspond to a multi-core Central Processing Unit (CPU) comprising of multiple CPUs or a multi-core Digital Signal Processor (DSP) comprising of multiple DSPs to practice the present invention.

First claim

The invention claimed is:

1. A method for video decoding using multiple processors with dynamic load balancing, the method comprising:
determining multiple processing modules associated with decoding a video bitstream, wherein the multiple processing modules comprise distinct processing modules including a prediction module;
configuring said multiple processors to perform the multiple processing modules by mapping the multiple processing modules to said multiple processors, wherein one or more buffer queues are used among said multiple processing modules; and
wherein said multiple processors comprise a first processor configured to generate output data to said one or more buffer queues and a second processor configured to retrieve input data from said one or more buffer queues, wherein said mapping the multiple processing modules to said multiple processors is based on multiple load configurations, wherein switching among the multiple load configurations is based on the level of said one or more buffer queues.

2. The method of claim 1 , wherein the prediction module comprises an intra prediction sub-module, an inter prediction sub-module, motion vector determination and intra mode determination.

3. The method of claim 2 , wherein said mapping the prediction module to said multiple processors is based on different levels of said one or more buffer queues.

4. The method of claim 1 , wherein output data after processing by the prediction module is stored in said one or more buffer queues.

5. The method of claim 1 , wherein said decoding the video bitstream is performed on a macroblock basis.

6. The method of claim 5 , wherein the multiple processing modules comprise a Variable Length Decoder (VLD) module, and wherein motion vector determination and intra mode determination of the prediction module and the VLD module associated with each macroblock are performed on a same processor of said multiple processors.

7. The method of claim 5 , wherein the multiple processing modules comprise a deblocking module to perform deblocking process on video data processed by the prediction module, wherein intra prediction of the prediction module refers to the video data above each macroblock processed by the prediction module before the deblocking process, and the deblocking module is performed on each macroblock later than the prediction module by at least one macroblock.

8. The method of claim 5 , wherein the multiple processing modules comprise a deblocking module to perform deblocking process on video data processed by the prediction module, wherein intra prediction of the prediction module refers to the video data above each macroblock processed by the prediction module before the deblocking process, wherein previous pixels processed by the prediction module are backed up before the deblocking module is performed on each macroblock, and wherein the previous pixels comprise bottom pixels of proceeding macroblocks and a number of proceeding macroblocks is at least one macroblock row.

9. The method of claim 5 , wherein if an intra macroblock is assigned to one of said multiple processors, all subsequent intra macroblocks of said the intra macroblock in a same macroblock row are assigned to said one of said multiple processors.

10. The method of claim 1 , wherein the multiple load configurations comprise a first load configuration, a second load configuration and a third load configuration, wherein the first load configuration assigns a Variable Length Decoder (VLD) module to one processor, the second load configuration assigns the VLD module, an Inverse Quantization (IQ) module and an Inverse Transform (IT) module to said one processor, and the third load configuration assigns the VLD module, the IQ module, the IT module and the prediction module to said one processor.

11. The method of claim 1 , wherein said multiple processors correspond to a multi-core Central Processing Unit (CPU) comprising of multiple CPUs or a multi-core Digital Signal Processor (DSP) comprising of multiple DSPs.

12. The method of claim 1 , wherein the multiple processing modules comprise an Inverse Quantization (IQ) module and an Inverse Transform (IT) module.

13. A non-transitory computer readable medium storing a computer program for decoding a video bitstream using multiple processors with dynamic load balancing, the computer program comprising sets of instructions for:
determining multiple processing modules associated with decoding the video bitstream, wherein the multiple processing modules comprise distinct processing modules including a prediction module;
configuring said multiple processors to perform the multiple processing modules by mapping the multiple processing modules to said multiple processors, wherein one or more buffer queues are used among said multiple processing modules; and
wherein said multiple processors comprise a first processor configured to generate output data to said one or more buffer queues and a second processor configured to retrieve input data from said one or more buffer queues, wherein said mapping the multiple processing modules to said multiple processors is based on multiple load configurations, wherein switching among the multiple load configurations is based on the level of said one or more buffer queues.

14. The non-transitory computer readable medium of claim 13 , wherein the prediction module comprises an intra prediction sub-module, an inter prediction sub-module, motion vector determination and intra mode determination.

15. The non-transitory computer readable medium of claim 14 , wherein said mapping the prediction module to said multiple processors is based on different levels of said one or more buffer queues.

16. The non-transitory computer readable medium of claim 13 , wherein output data after processing by the prediction module is stored in said one or more buffer queues.

17. The non-transitory computer readable medium of claim 13 , wherein said decoding the video bitstream is performed on a macroblock basis.

18. The non-transitory computer readable medium of claim 17 , wherein the multiple processing modules comprise a variable Length Decoder (VLD) module, and wherein motion vector determination intra mode determination of the prediction module and the VLD module associated with each macroblock are performed on a same processor of said multiple processors.

19. The non-transitory computer readable medium of claim 17 , wherein the multiple processing modules comprise a deblocking module to perform deblocking process on video data processed by the prediction module, wherein intra prediction of the prediction module refers to the video data above each macroblock processed by the prediction module before the deblocking process, and the deblocking module is performed on each macroblock later than the prediction module by at least one macroblock.

20. The non-transitory computer readable medium of claim 17 , wherein the multiple processing modules comprise a deblocking module to perform deblocking process on video data processed by the prediction module, wherein intra prediction of the prediction module refers to the video data above each macroblock processed by the prediction module before the deblocking process, wherein previous pixels processed by the prediction module are backed up before the deblocking module is performed on each macroblock, and wherein the previous pixels comprise bottom pixels of proceeding macroblocks and a number of proceeding macroblocks is at least one macroblock row.

21. The

Assignees

• Chen Ding-Yun
• Ho Cheng-Tsai
• Ju Chi-Cheng
• Tsai Chung-Hung
• Mediatek Inc

Inventors

• Chen Ding-Yun
• Ho Cheng-Tsai
• Ju Chi-Cheng
• Tsai Chung-Hung

Classifications

• H04N19/61

  in combination with predictive coding · CPC title

• H04N19/436 Primary

  using parallelised computational arrangements · CPC title