Built-in redundancy scheme for communication system on chip

Patent metadata

Field	Value
Publication number	US-9621280-B2
Application number	US-201615223326-A
Country	US
Kind code	B2
Filing date	Jul 29, 2016
Priority date	Jul 11, 2013
Publication date	Apr 11, 2017
Grant date	Apr 11, 2017

Abstract

In an example, the present invention includes an integrated system on chip device. The device has a redundancy block is configured to add at least redundancy bit as a function of one or more data bits associated with data for data error detection and correction data. In an example, the driver module is coupled to the signal processing blocking using a uni-directional multi-lane bus configured with N lanes, whereupon N is greater than M such that a difference between N and M represents a redundant lane or lanes. The device also has a mapping block configured to associate the M lanes to a plurality of selected laser devices for a silicon photonics device.

First claim

What is claimed is:

1. A communication system comprising:
a monolithically integrated system on chip device configured for a multi-rate and selected format of data communication, the device comprising:
a silicon substrate member;
a data input/output interface provided on the substrate member and configured for a predefined data rate and protocol, the data input/output interface being configured for a number of lanes numbered from four to one hundred and fifty;
an input/output block provided on the substrate member and coupled to the data input/output interface, the input/output block comprising a SerDes block, a CDR block, a compensation block, and an equalizer block, the SerDes block being configured to convert a first data stream of X into a second data stream of Y, each of the first data stream having a first predefined data rate at a first clock rate and each of the second data stream having a second predefined data rate at a second clock rate;
a signal processing block provided on the substrate member and coupled to the input/output block, the signal processing block configured to the input/output block using a bi-direction bus in an intermediary protocol;
a driver module provided on the substrate member and coupled to the signal processing block, the driver module coupled to the signal processing blocking using a uni-directional multi-lane bus configured with N lanes;
a mapping block configured to associate M lanes to a plurality of selected laser devices for a silicon photonics device, whereupon N is greater than M such that a difference between N and M represents a redundant lane or lanes;
a driver interface provided on the substrate member and coupled to the driver module and configured to be coupled to the silicon photonics device, the driver interface comprising a slicer block and being configured to transmit output data in a multi-level pulse amplitude modulation (PAM) format;
a receiver module comprising a TIA block provided on the substrate member and to be coupled to the silicon photonics device using the multi-level pulse amplitude modulation format, and coupled to the signal processing block to communicate information to the input output block for transmission through the data input/output interface;
a communication block provided on the substrate member and operably coupled to the input/output block, the signal processing block, the driver block, and the receiver block;
a communication interface coupled to the communication block;
a control block provided on the substrate member and coupled to the communication block; and
a redundancy block configured to add at least a redundancy bit as a function of one or more data bits associated with data for data error detection and correction, wherein the redundancy block is configured for at least data error detection/correction coding selected from at least one of a Checksum or Cyclic Redundancy Check (CRC); and
a network coupled to the monolithically integrated system on the chip.

2. The system of claim 1 wherein the signal processing block comprises a digital signal processing block, a framing block, a protocol block, and the redundancy block.

3. The system of claim 1 wherein the driver module is selected from a current drive or a voltage driver.

4. The system of claim 1 wherein the driver module is a differential driver.

5. The system of claim 1 wherein the redundancy block is configured with redundant bits, the redundant bits are configured as complex functions of original data bits.

6. The system of claim 1 wherein the silicon photonic device is configured to convert the output data into an output transport data in a WDM signal.

7. The system of claim 1 wherein the control block is configured to initiate a laser bias or a modulator bias.

8. The system of claim 1 wherein the control block is configured for laser bias and power control of the silicon photonics device.

9. The system of claim 1 wherein the control block is configured with a thermal tuning or carrier tuning device each of which is configured on the silicon photonics device.

10. A device configured for a multi-rate and selected format of data communication, the device comprising:
a substrate member;
a data input/output interface provided on the substrate member and configured for a predefined data rate and protocol, the data input/output interface being configured for a number of lanes numbered from four to one hundred and fifty;
an input/output block provided on the substrate member and coupled to the data input/output interface, the input/output block comprising a SerDes block, a CDR block, a compensation block, and an equalizer block, the SerDes block being configured to convert a first data stream of X into a second data stream of Y, each of the first data stream having a first predefined data rate at a first clock rate and each of the second data stream having a second predefined data rate at a second clock rate;
a signal processing block provided on the substrate member and coupled to the input/output block, the signal processing block configured to the input/output block using a bi-direction bus in an intermediary protocol;
a driver module provided on the substrate member and coupled to the signal processing block, the driver module coupled to the signal processing blocking using a uni-directional multi-lane bus configured with N lanes;
a mapping block configured to associate M lanes to a plurality of selected laser devices for a silicon photonics device, whereupon N is greater than M such that a difference between N and M represents a redundant lane or lanes;
a driver interface provided on the substrate member and coupled to the driver module and configured to be coupled to the silicon photonics device, the driver interface comprising a slicer block and being configured to transmit output data in a multi-level pulse amplitude modulation (PAM) format;
a receiver module comprising a TIA block provided on the substrate member and to be coupled to the silicon photonics device using the multi-level pulse amplitude modulation format, and coupled to the signal processing block to communicate information to the input output block for transmission through the data input/output interface;
a communication block provided on the substrate member and operably coupled to the input/output block, the signal processing block, the driver block, and the receiver block;
a communication interface coupled to the communication block;
a control block provided on the substrate member and coupled to the communication block; and
a redundancy block configured to add at least a redundancy bit as a function of one or more data bits associated with data for data error detection and correction; and the function is configured as a complex function of the one or more data bits, wherein the redundancy block is configured for at least data error detection/correction coding selected from at least one of a Checksum or Cyclic Redundancy Check (CRC).

11. The device of claim 10 wherein the signal processing block comprises a digital signal processing block, a framing block, a protocol block, and the redundancy block.

12. The device of claim 10 wherein the driver module is selected from a current drive or a voltage driver or a differential driver.

13. The device of claim 10 wherein the redundancy block is configured with redundant bits, the redundant bits are configured as complex functions of original data bits.

14. A chip device, the device comprising:
a silicon substrate member;
a data input/output interface provided on the substrate member and configured for a predefined data rate and protocol, the data inpu

Assignees

• Inphi Corp

Inventors

• Nagarajan Radhakrishnan L

Classifications

• H04B10/801 Primary

  using optical interconnects, e.g. light coupled isolators, circuit board interconnections · CPC title

• H04B10/69

  Electrical arrangements in the receiver · CPC title

• H04B10/40 Primary

  Transceivers · CPC title

• G02B6/00

  Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings · CPC title

• H04J14/02

  Wavelength-division multiplex systems · CPC title