Offset correction for sense amplifier

Patent metadata

Field	Value
Publication number	US-9621176-B2
Application number	US-201615277076-A
Country	US
Kind code	B2
Filing date	Sep 27, 2016
Priority date	Jul 13, 2015
Publication date	Apr 11, 2017
Grant date	Apr 11, 2017

Abstract

The present invention is directed to data communication. More specifically, embodiments of the present invention provide an offset correction technique for a SERDES system. A CTLE module for receiving input data signal is set to an isolation mode, and one or more sense amplifiers perform data sampling asynchronously during the isolation mode. During the isolation mode, CLTE(s) that are not directly connected to the sense amplifiers are shut. Data sampled during the isolation mode are used to determine an offset value that is later used in normal operation of the SERDES system. There are other embodiments as well.

First claim

What is claimed is:

1. An apparatus comprising:
an equalizer module comprising a first Continuous Time Linear Equalizer (CTLE) and a second CTLE, an output of the first CTLE being connected to an input of the second CTLE, the second CTLE generating a first equalizer output signal from an input signal, the input signal being characterized by a first sampling frequency;
a Digital to Analog Converter (DAC) generating an offset correction signal determined at an isolation mode of the equalizer module;
a first sense amplifier generating data samples by sampling the equalizer output signal from the second CTLE at the first sampling frequency using the offset correction signal;
wherein during the isolation mode:
the first CTLE is shut and the second CTLE operates in a common mode and generates a second equalizer output signal;
the first sense amplifier generates a predetermined number of samples at a second sampling frequency different from the first sampling frequency; and
the offset correction signal is determined using the predetermined number of samples.

2. The apparatus of claim 1 further comprising a second sense amplifier, wherein the second sense amplifier is an edge sense amplifier.

3. The apparatus of claim 1 further comprising a Demultiplexor (DEMUX) for selecting the data samples from the first sense amplifier.

4. The apparatus of claim 1 wherein the equalizer module further comprises a third CTLE, output of the third CTLE being coupled to an input of the first CTLE, the third CTLE being shut during the isolation mode.

5. The apparatus of claim 1 further comprising a second sense amplifier, wherein the first sense amplifier comprises a data sense amplifier and the second sense amplifier comprises an edge amplifier.

6. The apparatus of claim 1 further comprising a digital correction module configured to determine and provide a digital offset correction value input to the DAC.

7. The apparatus of claim 6 wherein the digital correction module comprises a digital filter.

8. The apparatus of claim 7 wherein the digital filter is configured to remove capacitive coupling effects.

9. The apparatus of claim 7 wherein the digital filter is configured to provide offset correction.

10. The apparatus of claim 1 further comprising a Phase-Lock Loop (PLL) providing a clock signal for the first sense amplifier.

11. The apparatus of claim 10 further comprising a decoder between the first sense amplifier and the PLL.

12. The apparatus of claim 1 wherein the during the isolation mode the first sense amplifier generates the predetermined number of samples in an asynchronous manner.

13. The apparatus of claim 1 wherein the first sense amplifier generates data samples by sampling the equalizer output in a synchronous manner.

14. An apparatus comprising:
an equalizer module comprising a first Continuous Time Linear Equalizer (CTLE) and a second CTLE, an output of the first CTLE being connected to an input of the second CTLE, the second CTLE being configured to generate an equalizer output signal from an input signal, the input signal being characterized by a first sampling frequency;
an offset correction module being configured to generate an offset correction signal;
a first sense amplifier being configured to generate data samples by sampling the equalizer output signal from the second CTLE at the first sampling frequency using the offset correction signal;
a second sense amplifier being configured to process the equalizer output signal at the first sampling frequency;
wherein during an isolation mode:
the first CTLE is shut and the second CTLE operates in a common mode and generates a second equalizer output signal;
the first sense amplifier generates a predetermined number of samples at a second sampling frequency different from the first sampling frequency; and
the offset correction module determines the offset correction signal using at least the predetermined number of samples.

15. The apparatus of claim 14 wherein the offset correction module comprises a digital correction module including a digital filter.

16. The apparatus of claim 15 wherein the digital filter is configured to remove capacitive coupling effects.

17. The apparatus of claim 15 wherein the digital filter is configured to provide offset correction.

18. The apparatus of claim 14 wherein the offset correction module comprises a Digital to Analog Converter (DAC).

19. The apparatus of claim 14 wherein the first sense amplifier comprises a data sense amplifier and the second sense amplifier comprises an edge amplifier.

20. The apparatus of claim 14 wherein the offset correction module comprises a Demultiplexor (DEMUX) for selecting the data samples from the first sense amplifier.

Assignees

• Inphi Corp

Inventors

• Mishra Parmanand
• Forey Simon

Classifications

• H04L25/03878 Primary

  Line equalisers; line build-out devices · CPC title

• H03M1/1023 Primary

  Offset correction (H03M1/1019 takes precedence; removal of offset already present on the analogue input signal H03M1/1295) · CPC title

• H04L25/03057

  with a recursive structure (H04L25/03031 takes precedence) · CPC title

• H03M1/66

  Digital/analogue converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title