Wide frequency/voltage-ratio buffer with adaptive power consumption

Patent metadata

Field	Value
Publication number	US-9621166-B1
Application number	US-201514862473-A
Country	US
Kind code	B1
Filing date	Sep 23, 2015
Priority date	Sep 23, 2015
Publication date	Apr 11, 2017
Grant date	Apr 11, 2017

Abstract

Certain aspects of the present disclosure provide methods and apparatus (e.g., a level shifter) for buffering an oscillating signal generated by an oscillator. One example apparatus generally includes an amplifier having a first amplification stage configured to amplify the oscillating signal generated by the oscillator and a second amplification stage configured to amplify an inverse of the oscillating signal generated by the oscillator; and a sensing circuit configured to adjust an operational bandwidth of the amplifier based on a frequency of the oscillating signal.

First claim

What is claimed is:

1. An apparatus for buffering an oscillating signal generated by an oscillator, comprising:
an amplifier comprising:
a first amplification stage configured to amplify the oscillating signal generated by the oscillator and having an output coupled to a first transistor, wherein the first amplification stage comprises a second transistor connected with a third transistor, a gate of the second transistor and a gate of the third transistor coupled to the oscillator to receive the oscillating signal; and
a second amplification stage configured to amplify an inverse of the oscillating signal generated by the oscillator, wherein an output of the second amplification stage is configured to drive the first transistor; and

a sensing circuit configured to adjust an operational bandwidth of the amplifier based on a frequency of the oscillating signal.

2. The apparatus of claim 1 , wherein the operational bandwidth of the amplifier is adjusted by adjusting an output switching speed of the amplifier.

3. The apparatus of claim 1 , wherein the sensing circuit comprises a current source and is further configured to:
adjust a current sourced by the current source based on the frequency of the oscillating signal; and
bias at least one of the first amplification stage or the second amplification stage with the adjusted sourced current.

4. The apparatus of claim 1 , wherein the sensing circuit comprises a current sensing circuit configured to sense a current input to the oscillator and to output a bias current for at least one of the first amplification stage or the second amplification stage based on the sensed input current.

5. The apparatus of claim 1 , wherein:
the sensing circuit comprises a voltage sensing circuit configured to sense a voltage input to the oscillator;
the voltage sensing circuit is configured to adjust a bias current for at least one of the first amplification stage or the second amplification stage based on the sensed input voltage; and
the frequency of the oscillating signal is adjusted based on the voltage input to the oscillator.

6. The apparatus of claim 1 , further comprising a latch circuit configured to level shift an amplitude of the amplified oscillating signal.

7. The apparatus of claim 6 , wherein:
an
the latch circuit is configured to level shift the amplified oscillating signal based on a voltage at a node connected to a drain of the second transistor and a drain of the third transistor.

8. The apparatus of claim 1 , wherein the first transistor is connected in parallel with the second transistor.

9. The apparatus of claim 8 , wherein:
the second amplification stage comprises a fourth transistor connected with a fifth transistor;
a gate of the fourth transistor and a gate of the fifth transistor are coupled to the oscillator and configured to receive the inverse of the oscillating signal generated by the oscillator; and
the output of the second amplification stage is at a node connected to at least one of a drain of the fourth transistor or a drain of the fifth transistor.

10. The apparatus of claim 8 , wherein the second amplification stage comprises a voltage-limiting circuit configured to limit a voltage of the output of the second amplification stage.

11. The apparatus of claim 1 , wherein a periodic signal output by the latch circuit is configured to oscillate between a first voltage level and a second voltage level independent of the frequency of the oscillating signal.

12. A method for buffering an oscillating signal generated by an oscillator, comprising:
adjusting an operational bandwidth of an amplifier based on a frequency of the oscillating signal;
amplifying the oscillating signal via a first amplification stage of the amplifier;
amplifying an inverse of the oscillating signal via a second amplification stage of the amplifier, wherein the amplified inverse of the oscillating signal is used to drive at least a portion of the first amplification stage, wherein the at least the portion of the first amplification stage comprises a first transistor, the first amplification stage comprising a second transistor connected with a third transistor, and wherein a gate of the second transistor and a gate of the third transistor are coupled to the oscillator for receiving the oscillating signal.

13. The method of claim 12 , wherein adjusting the operational bandwidth of the amplifier comprises adjusting an output switching speed of the amplifier.

14. The method of claim 12 , further comprising:
adjusting a sourced current based on the frequency of the oscillating signal; and
biasing at least one of the first amplification stage or the second amplification stage using the adjusted sourced current.

15. The method of claim 12 , further comprising:
sensing a current input to the oscillator; and
outputting a bias current for at least one of the first amplification stage or the second amplification stage based on the sensed input current.

16. The method of claim 12 , further comprising:
sensing a voltage input to the oscillator, wherein the frequency of the oscillating signal is adjusted based on the sensed input voltage; and
adjusting a current used to bias at least one of the first amplification stage or the second amplification stage based on the sensed input voltage.

17. The method of claim 12 , further comprising level shifting an amplitude of the amplified oscillating signal.

18. The method of claim 17 , wherein:
level shifting the amplitude of the amplified oscillating signal comprises level shifting the amplitude based on a voltage at a node connected to a drain of the second transistor and a drain of the third transistor.

19. The method of claim 12 , wherein:
the second amplification stage comprises a fourth transistor connected in cascode with a fifth transistor;
a gate of the fourth transistor and a gate of the fifth transistor are coupled to the oscillator and configured to receive the inverse of the oscillating signal generated by the oscillator; and
an output of the second amplification stage is at a node connected to at least one of a drain of the fourth transistor or a drain of the fifth transistor.

20. The method of claim 12 , further comprising limiting a voltage of an output of the second amplification stage with a voltage-limiting circuit connected between the gate of the first transistor and a source of the first transistor.

21. A level shifter for adjusting an amplitude of an oscillating signal generated by an oscillator, comprising:
a first amplifier circuit configured to amplify the oscillating signal, wherein an operational bandwidth of the first amplifier circuit is adjusted based on a frequency of the oscillating signal, wherein the first amplifier circuit comprises a first transistor connected with a second transistor, and wherein a gate of the first transistor and a gate of the second transistor are coupled to the oscillator to receive the oscillating signal;
a current sensing circuit configured to sense a current input to the oscillator and output a bias current for the first amplifier circuit based on the sensed input current; and
a latch circuit configured to level shift the amplitude of the amplified oscillating signal.

22. The level shifter of claim 21 , wherein:
the latch circuit is configured to level shift the amplified oscillating signal based on a voltage at a node connected to a drain of the first transistor and a drain of the second transistor.

Assignees

• Qualcomm Inc

Inventors

• Zargham Mohammad Meysam
• Roham Masoud
• Dai Liang

Classifications

• H03K19/018528 Primary

  with at least one differential stage · CPC title

• H03F3/45179

  using MOSFET transistors as the active amplifying circuit (H03F3/45278 takes precedence) · CPC title

• H03F3/45475

  using IC blocks as the active amplifying circuit · CPC title

• H03F2200/444

  Diode used as protection means in an amplifier, e.g. as a limiter or as a switch · CPC title

• H03F1/42

  Modifications of amplifiers to extend the bandwidth · CPC title