Active load circuit and semiconductor integrated circuit

Patent metadata

Field	Value
Publication number	US-9621116-B2
Application number	US-201514844188-A
Country	US
Kind code	B2
Filing date	Sep 3, 2015
Priority date	Mar 9, 2015
Publication date	Apr 11, 2017
Grant date	Apr 11, 2017

Abstract

According to one embodiment, there is provided an active load circuit including a first transistor, a second transistor, a first resistor, a second resistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a line. The third transistor is placed between the first transistor and the first reference node. The fourth transistor is placed between the second transistor and the first reference node. The seventh transistor is placed between the fifth transistor and the first reference node. The eighth transistor is placed between the sixth transistor and the first reference node. A line connecting a fifth node between the fifth transistor and the seventh transistor and a sixth node between the sixth transistor and the eighth transistor.

First claim

What is claimed is:

1. An active load circuit comprising:
a first transistor placed between a first node and a first reference node;
a second transistor placed between a second node and the first reference node;
a first resistor of which one end is connected to gate of the first transistor and the other end is connected to the first node;
a second resistor of which one end is connected to gate of the second transistor and the other end is connected to the second node;
a third transistor placed between the first transistor and the first reference node;
a fourth transistor placed between the second transistor and the first reference node;
a fifth transistor, together with the second transistor, forming a current mirror circuit and placed between a third node and the first reference node;
a sixth transistor, together with the first transistor, forming a current mirror circuit and placed between a fourth node and the first reference node;
a seventh transistor placed between the fifth transistor and the first reference node;
an eighth transistor placed between the sixth transistor and the first reference node; and
a line connecting a fifth node between the fifth transistor and the seventh transistor and a sixth node between the sixth transistor and the eighth transistor.

2. The active load circuit according to claim 1 , wherein the first, second, fifth, and sixth transistors have a dimension even for each transistor.

3. The active load circuit according to claim 1 , wherein the third, fourth, seventh, and eighth transistors are each configured to operate in a linear region.

4. The active load circuit according to claim 1 , wherein the gate of the first transistor, of the third transistor, and of the eighth transistor are connected to each other, and
wherein the gate of the second transistor, of the fourth transistor, and of the seventh transistor are connected to each other.

5. The active load circuit according to claim 1 , further comprising a bias circuit connected to gate of the third transistor, of the fourth transistor, of the seventh transistor, and of the eighth transistor.

6. The active load circuit according to claim 5 , wherein the bias circuit has:
a current source;
a first replica transistor connected to the current source and having characteristics equivalent to those of the first transistor; and
a second replica transistor placed between the first replica transistor and the first reference node and having characteristics equivalent to those of the second transistor.

7. The active load circuit according to claim 6 , wherein the first replica transistor has a dimension equivalent to that of the first transistor, and
wherein the second replica has a dimension equivalent to that of the second transistor.

8. The active load circuit according to claim 1 , further comprising:
a third resistor of which one end is connected to the gate of the first transistor and of the third transistor and another end is connected to an intermediate node; and
a fourth resistor of which one end is connected to the gate of the second transistor and of the fourth transistor and another end is connected to the intermediate node;
wherein the intermediate node is connected to gate of the seventh transistor and of the eighth transistor.

9. The active load circuit according to claim 8 , wherein resistance of the third resistor and resistance of the fourth resistor are even.

10. A semiconductor integrated circuit comprising:
a one-stage amplifier having the active load circuit according to claim 1 as a first gain stage between a first input stage to which a first differential input pair is connected and a first differential output pair; and
a two-stage amplifier having two stages of a second gain stage and a third gain stage between a second input stage to which the first differential input pair is connected and the first differential output pair,
wherein the third gain stage has:
a ninth transistor, of a conductivity type opposite to that of the fifth transistor, of which drain is connected to drain of the fifth transistor; and
a tenth transistor, of a conductivity type opposite to that of the sixth transistor, of which drain is connected to drain of the sixth transistor.

11. The semiconductor integrated circuit according to claim 10 , wherein the third gain stage further has:
a first capacitance element of which one end is connected to one output of the first differential output pair;
a first switch of which one end is connected to the other end of the first capacitance element and another end is connected to the second gain stage;
a second capacitance element of which one end is connected to the other output of the first differential output pair; and
a second switch of which one end is connected to the other end of the second capacitance element and another end is connected to the second gain stage,
wherein the semiconductor integrated circuit further comprises a common-mode feedback circuit connected between an intermediate node of the first differential output pair and the first differential output pair, and
wherein the common-mode feedback circuit has:
an eleventh transistor of which one of source and drain is connected to one output of the first differential output pair and another end is connected to the first reference node;
a third switch of which one end is connected to drain of the eleventh transistor and another end is connected to one output of the first differential output pair;
a twelfth transistor of which one of source and drain is connected to the other output of the first differential output pair and another end is connected to the first reference node;
a fourth switch of which one end is connected to drain of the twelfth transistor and another end is connected to the other output of the first differential output pair;
a thirteenth transistor of which one of source and drain is connected to one output of the first differential output pair and another end is connected to a second reference node;
a fifth switch of which one end is connected to drain of the thirteenth transistor and another end is connected to one output of the first differential output pair;
a fourteenth transistor of which one of source and drain is connected to the other output of the first differential output pair and another end is connected to the second reference node; and
a sixth switch of which one end is connected to drain of the fourteenth transistor and another end is connected to another output of the first differential output pair.

12. The semiconductor integrated circuit according to claim 10 , wherein the ninth transistor is placed between the fifth transistor and the second reference node, and
wherein the tenth transistor is placed between the sixth transistor and the second reference node.

13. The semiconductor integrated circuit according to claim 10 , wherein a node between the fifth transistor and the ninth transistor is connected to one output of the first differential output pair, and
wherein a node between the sixth transistor and the tenth transistor is connected to another output of the first differential output pair.

14. The semiconductor integrated circuit according to claim 10 , wherein the second gain stage has:
a fifteenth transistor placed between a seventh node and the second reference node;
a sixteenth transistor placed between an eighth node and the second reference node;
a fifth resistor of which one end is connected to the seventh node and another end is connected to gate of the fifteenth transistor and of the sixteenth transistor; and
a sixth resistor of which one end is conn

Assignees

• Toshiba Kk

Inventors

• Ito Rui
• Matsui Naohiro

Classifications

• H03F2203/45424

  the CMCL comprising a comparator circuit · CPC title

• H03F3/45183

  Long tailed pairs (H03F3/4521, H03F3/45237 take precedence) · CPC title

• H03F3/45659

  Controlling the loading circuit of the differential amplifier · CPC title

• H03F1/42 Primary

  Modifications of amplifiers to extend the bandwidth · CPC title

• H03F3/4521

  Complementary long tailed pairs having parallel inputs and being supplied in parallel · CPC title