Methods of forming contact feature

Patent metadata

Field	Value
Publication number	US-9620628-B1
Application number	US-201615204848-A
Country	US
Kind code	B1
Filing date	Jul 7, 2016
Priority date	Jul 7, 2016
Publication date	Apr 11, 2017
Grant date	Apr 11, 2017

Abstract

A method to fabricate a semiconductor device includes forming a semiconductor fin on a substrate; forming a dummy gate material layer over the semiconductor fin; forming a contact hole in the dummy gate material layer; forming a source/drain feature in the contact hole; forming a contact feature on the source/drain feature within the contact hole; and replacing a dummy gate that is formed of the dummy gate material layer with a metal gate.

First claim

What is claimed is:

1. A method comprising:
forming a semiconductor fin on a substrate;
forming a dummy gate material layer over the semiconductor fin;
forming a contact hole in the dummy gate material layer;
forming a source/drain feature in the contact hole;
forming a contact feature on the source/drain feature within the contact hole; and
replacing a dummy gate that is formed of the dummy gate material layer with a metal gate.

2. The method of claim 1 , wherein the dummy gate material layer includes a poly-semiconductor layer and a dielectric layer formed over the poly-semiconductor layer.

3. The method of claim 1 , wherein forming the contact hole in the dummy gate material layer includes:
etching the dummy gate material layer thereby exposing the semiconductor fin through the contact hole;
depositing a spacer layer over the semiconductor fin and sidewalls of the contact hole; and
etching a portion of the spacer layer that overlays the semiconductor fin.

4. The method of claim 3 , wherein the spacer layer is formed of a material that is selected from the group consisting of silicon nitride and silicon carbonitride.

5. The method of claim 1 , wherein forming the source/drain feature in the contact hole includes epitaxially growing the source/drain feature on the semiconductor fin.

6. The method of claim 1 , wherein forming the contact feature on the source/drain feature within the contact hole includes:
depositing a conductive material layer over the source/drain feature thereby filling the contact hole with the conductive material layer;
recessing the conductive material layer; and
forming a dielectric layer over the recessed conductive material layer.

7. The method of claim 1 , further comprising forming a patterned material layer over the dummy gate material layer, the patterned material layer having an opening that exposes a portion of the dummy gate material layer, and
wherein replacing the dummy gate that is formed of the dummy gate material layer with the metal gate includes removing the exposed portion of the dummy gate material layer.

8. The method of claim 1 , wherein replacing the dummy gate with the metal gate includes:
removing the dummy gate from the semiconductor fin;
forming a gate dielectric layer over the semiconductor fin; and
forming a metal layer over the gate dielectric layer.

9. The method of claim 1 , further comprising:
recessing the metal gate;
forming a dielectric layer over the recessed metal gate; and
planarizing the dielectric layer thereby exposing the contact feature in the contact hole.

10. A method comprising:
forming a semiconductor fin on a substrate;
forming a dummy gate material layer over the semiconductor fin;
forming a contact hole in the dummy gate material layer;
forming a source/drain feature in the contact hole;
forming a contact feature on the source/drain feature within the contact hole;
removing a portion of the dummy gate material layer to form a trench; and
forming a gate electrode material layer within the trench.

11. The method of claim 10 , wherein the dummy gate material layer includes a poly-semiconductor layer and a dielectric layer formed over the poly-semiconductor layer.

12. The method of claim 10 , wherein forming the contact hole in the dummy gate material layer includes:
etching the dummy gate material layer thereby exposing the semiconductor fin through the contact hole; and
depositing a spacer layer over the semiconductor fin and sidewalls of the contact hole.

13. The method of claim 12 , wherein the spacer layer is formed of a material that is selected from the group consisting of silicon nitride and silicon carbonitride.

14. The method of claim 10 , wherein forming the source/drain feature in the contact hole includes epitaxially growing the source/drain feature on the semiconductor fin.

15. The method of claim 10 , wherein forming the contact feature on the source/drain feature within the contact hole includes:
depositing a conductive material layer over the source/drain feature within the contact hole;
recessing the conductive material layer; and
forming a dielectric layer over the recessed conductive material layer.

16. The method of claim 10 , wherein forming the gate electrode material layer within the trench includes forming a metal material layer within the trench.

17. The method of claim 16 , wherein removing the portion of the dummy gate material layer to form the trench includes removing the portion of the dummy gate material layer to thereby expose a portion of the fin structure within the trench.

18. The method of claim 17 , further comprising forming a gate dielectric layer on the exposed portion of the fin structure;
recessing the gate electrode material layer;
forming a dielectric layer over the recessed gate electrode material layer; and
planarizing the dielectric layer thereby exposing the contact feature.

19. A method, comprising:
forming a semiconductor fin on a substrate;
forming a dummy gate material layer over the semiconductor fin;
forming a contact hole in the dummy gate material layer to expose a portion of the semiconductor fin;
forming a source/drain feature on the exposed portion of the semiconductor fin;
forming a contact feature on the source/drain feature;
removing a portion of the dummy gate material layer to form a trench; and
forming a metal gate electrode within the trench.

20. The method of claim 19 , further comprising forming a spacer layer within the trench, and
wherein forming the contact hole in the dummy gate material layer to expose the portion of the semiconductor fin includes removing a portion of the spacer layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Huang Gin-Chen
• Huang Hui-Chi
• Lu Yung-Cheng

Classifications

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/6905

  being a silicon carbide or silicon carbonitride and not containing oxygen, e.g. SiC or SiC:H · CPC title

• H10P50/283

  by chemical means · CPC title

• H10D64/011

  of electrodes ohmically coupled to a semiconductor · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title