Display panel motherboard and manufacturing method thereof
US-2015313021-A1 · Oct 29, 2015 · US
Display substrate and fabricating method thereof, mask plate, and mask plate group
US9620537B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9620537-B2 |
| Application number | US-201615188936-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jun 21, 2016 |
| Priority date | May 4, 2014 |
| Publication date | Apr 11, 2017 |
| Grant date | Apr 11, 2017 |
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- Title
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- Abstract
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Abstract
Official abstract text for this publication.
The present disclosure provides a display substrate and a mask plate, the display substrate comprising a plurality of sub display substrates, each of the sub display substrates comprising a plurality of pixel units, each pixel unit comprising a pixel electrode, a common electrode and a source-drain channel, wherein, from the center of the display substrate to the edge of the display substrate, the plurality of sub display substrates are arranged from large to small according to the overlapping area of the pixel electrode and the common electrode and/or the plurality of sub display substrates are arranged from small to large according to the width to length ratio of the source-drain channel of the sub display substrate. The present disclosure can avoid electrical badness of the sub display substrates located at the edges.
First claim
Opening claim text (preview).
The invention claimed is: 1. A mask plate for fabricating a display substrate, wherein the display substrate comprises a plurality of sub display substrates, each of the sub display substrates comprises a plurality of pixel units, and each of the pixel units comprises a pixel electrode, a common electrode and a source-drain channel, wherein the mask plate comprises a plurality of mask units which are in one-to-one correspondence with the plurality of sub display substrates, wherein the plurality of mask units are arranged in such a manner that areas of the mask units for forming the pixel electrodes or the common electrodes decrease from a center of the mask plate to an edge of the mask plate, or in such a manner that width to length ratios of the mask units for forming the source-drain channels increase from the center of the mask plate to the edge of the mask plate. 2. The mask plate according to claim 1 , wherein the mask plate is used for fabricating the pixel electrodes, wherein the common electrodes of the sub display substrates have same areas, and wherein the plurality of mask units are arranged in such a manner that areas of the mask units for forming the pixel electrodes decrease from the center of the mask plate to the edge of the mask plate. 3. The mask plate according to claim 1 , wherein the mask plate is used for fabricating the common electrodes, wherein the pixel electrodes of the sub display substrates have same areas, and wherein the plurality of mask units are arranged in such a manner that areas of the mask unit for forming the pixel electrodes decrease from the center of the mask plate to the edge of the mask plate. 4. The mask plate according to claim 1 , wherein the mask plate is used for fabricating the source-drain channels, and wherein the plurality of mask units are arranged in such a manner that width to length ratios of the mask units for forming the source-drain channels increase from the center of the mask plate to the edge of the mask plate. 5. The mask plate according to claim 1 , wherein the plurality of mask units are arranged in a matrix. 6. A mask plate group, comprising the mask plate according to claim 1 .
Assignees
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Classifications
using masks · CPC title
pixel · CPC title
in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title
Manufacturing of individual cells out of a plurality of cells, e.g. by dicing · CPC title
Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof · CPC title
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- What does patent US9620537B2 cover?
- The present disclosure provides a display substrate and a mask plate, the display substrate comprising a plurality of sub display substrates, each of the sub display substrates comprising a plurality of pixel units, each pixel unit comprising a pixel electrode, a common electrode and a source-drain channel, wherein, from the center of the display substrate to the edge of the display substrate, …
- Who is the assignee on this patent?
- Boe Technology Group Co Ltd, Chengdu Boe Optoelect Tech Co
- What technology area does this patent fall under?
- Primary CPC classification H01L27/1288. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Apr 11 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).