Semiconductor arrangement, method for producing a semiconductor module, method for producing a semiconductor arrangement and method for operating a semiconductor arrangement

Patent metadata

Field	Value
Publication number	US-9620459-B2
Application number	US-201414476241-A
Country	US
Kind code	B2
Filing date	Sep 3, 2014
Priority date	Sep 5, 2013
Publication date	Apr 11, 2017
Grant date	Apr 11, 2017

Abstract

A semiconductor arrangement includes upper and lower contact plates and basic chip assemblies. Each chip assembly has a semiconductor chip having a semiconductor body with upper and lower spaced apart sides. An individual upper main electrode and an individual control electrode are arranged on the upper side. The chip assemblies have either respectively a separate lower main electrode arranged on the lower side of the semiconductor chip of the corresponding basic chip assembly, or a common lower main electrode, which for each of the chip assemblies is arranged on the lower side of the semiconductor body of that chip assembly. An electrical current between the individual upper main electrode and the individual or common lower main electrode is controllable by its control electrode. The chip assemblies are connected to one another with a material bonded connection by a dielectric embedding compound, forming a solid assembly.

First claim

What is claimed is:

1. A semiconductor arrangement, comprising:
an upper contact plate and a lower contact plate;
a number of basic chip assemblies, each of which has:
a semiconductor chip having a semiconductor body, the semiconductor body having an upper side and a lower side opposite the upper side, and the upper side being separated from the lower side in a vertical direction;
an individual upper main electrode arranged on the upper side; and
an individual control electrode arranged on the upper side;
wherein the basic chip assemblies have either respectively a separate lower main electrode, which is arranged on the lower side of the semiconductor chip of the relevant basic chip assembly, or a common lower main electrode, which for each of the basic chip assemblies is arranged on the lower side of the semiconductor body of that basic chip assembly;
wherein, for each of the basic chip assemblies, an electrical current between the individual upper main electrode and the individual or common lower main electrode is controllable by means of its control electrode;
a dielectric embedding compound, by which the basic chip assemblies are connected to one another with a material bonded connection so as to form a solid assembly;
a control electrode interconnection structure, which is embedded in the solid assembly and which electrically conductively connects the control electrodes of the basic chip assemblies to one another.

2. The semiconductor arrangement of claim 1 , wherein:
(a) each of the basic chip assemblies has an electrically conductive upper compensating die, which is arranged on the side of the upper main electrode facing away from the semiconductor body and which is connected with a material bonded connection and electrically conductively connected by means of an upper connecting layer to the upper main electrode; or
(b) the basic chip assemblies have a common electrically conductive upper compensating plate, which for each of the basic chip assemblies is arranged on the side of the upper main electrode facing away from the semiconductor body and which is connected with a material bonded connection and electrically conductively connected by means of an upper connecting layer to the upper main electrode.

3. The semiconductor arrangement of claim 2 , wherein the upper connecting layer is formed as a solder layer or as an adhesive layer, or as a layer of a sintered metal powder.

4. The semiconductor arrangement of claim 2 , wherein:
in case (a) the upper compensating dies respectively have a linear thermal expansion coefficient of less than 11 ppm/K; or
in case (b) the upper compensating plate has a linear thermal expansion coefficient of less than 11 ppm/K.

5. The semiconductor arrangement of claim 2 , wherein:
in case (a) the upper compensating dies respectively have a thickness of at least 0.4 mm in the vertical direction; or
in case (b) the upper compensating plate has a thickness of at least 0.4 mm in the vertical direction.

6. The semiconductor arrangement of claim 2 , wherein the upper contact plate has a plane surface section on its side facing toward the lower contact plate, which:
in case (a) electrically contacts the side, of the upper compensating die of each of the basic chip assemblies, facing away from the semiconductor body; or
in case (b) electrically contacts the side of the upper compensating plate facing away from the semiconductor body.

7. The semiconductor arrangement of claim 2 , wherein the upper contact plate, on its side facing toward the lower contact plate:
in case has an upper contact elevation for each of the basic chip assemblies, which electrically contacts the side, of the upper compensating die of each of the basic chip assemblies, facing away from the semiconductor body; or
in case (b), has an upper contact elevation for each of the basic chip assemblies, which electrically contacts the side of the upper compensating plate facing away from the semiconductor body.

8. The semiconductor arrangement of claim 1 , wherein:
(c) each of the basic chip assemblies has an electrically conductive lower compensating die, which is arranged on the side of the lower main electrode facing away from the semiconductor body and is connected with a material bonded connection and electrically conductively by means of a lower connecting layer to the lower main electrode; or
(d) the basic chip assemblies have a common electrically conductive lower compensating plate, which for each of the basic chip assemblies is arranged on the side of the lower main electrode facing away from the semiconductor body and is connected with a material bonded connection and electrically conductively by means of a lower connecting layer to the lower main electrode.

9. The semiconductor arrangement of claim 8 , wherein the lower connecting layer is formed as a solder layer or as an adhesive layer, or as a layer of a sintered metal powder.

10. The semiconductor arrangement of claim 8 , wherein:
in case (c) the lower compensating dies respectively have a linear thermal expansion coefficient of less than 11 ppm/K; or
in case (d) the lower compensating plate has a linear thermal expansion coefficient of less than 11 ppm/K.

11. The semiconductor arrangement of claim 8 , wherein:
in case (c) the lower compensating dies respectively have a thickness of at least 0.4 mm in the vertical direction, or
in case (d) the lower compensating plate has a thickness of at least 0.4 mm in the vertical direction.

12. The semiconductor arrangement of claim 8 , wherein the lower contact plate has a plane surface section on its side facing toward the upper contact plate, which:
in case (c) electrically contacts the side, of the lower compensating die of each of the basic chip assemblies, facing away from the semiconductor body; or
in case (d) electrically contacts the side of the lower compensating plate facing away from the semiconductor body.

13. The semiconductor arrangement of claim 8 , wherein the lower contact plate, on its side facing toward the upper contact plate:
in case (c) has a lower contact elevation for each of the basic chip assemblies, which electrically contacts the side, of the lower compensating die of each of the basic chip assemblies, facing away from the semiconductor body; or
in case (d) has a lower contact elevation for each of the basic chip assemblies, which electrically contacts the side of the lower compensating plate facing away from the semiconductor body.

14. The semiconductor arrangement of claim 1 , further comprising a dielectric spacer ring arranged between the upper contact plate and the lower contact plate and surrounding the basic chip assemblies.

15. The semiconductor arrangement of claim 1 , further comprising an electrically conductive connection piece, which:
is embedded in the embedding compound;
is electrically conductively connected to the control electrodes by the control electrode interconnection structure;
is electrically contacted by a connection electrode which is passed through a feed-through formed in the embedding compound.

16. The semiconductor arrangement of claim 15 , wherein the feed-through extends starting from a side edge of the solid assembly in a direction perpendicular to the vertical direction into the embedding compound, as far as the connection piece.

17. The semiconductor arrangement of claim 1 , wherein the control electrode interconnection structure is formed as a printed circuit board, or as a structured metallization layer.

18. The semiconductor arrangement of claim 1 ,

Assignees

• Infineon Technologies Ag

Inventors

• Beer Gottfried
• Escher-Poeppel Irmgard
• Hoegerl Juergen
• Hohlfeld Olaf
• Kanschat Peter

Classifications

• H10W90/10

  Configurations of laterally-adjacent chips · CPC title

• H10W74/111

  the semiconductor body being completely enclosed · CPC title

• H10W72/07354

  changes in dispositions · CPC title

• H10W72/01904

  using temporary auxiliary members, e.g. using sacrificial coatings or handle substrates · CPC title

• H10W72/944

  Dispositions of multiple bond pads · CPC title