Semiconductor device packaging

Patent metadata

Field	Value
Publication number	US-9620457-B2
Application number	US-201314090570-A
Country	US
Kind code	B2
Filing date	Nov 26, 2013
Priority date	Nov 26, 2013
Publication date	Apr 11, 2017
Grant date	Apr 11, 2017

Abstract

A method of manufacturing a semiconductor device package includes encapsulating at least partially a plurality of semiconductor chips with encapsulating material to form an encapsulation body. The encapsulation body has a first main surface and a second main surface. At least one of a metal layer and an organic layer is formed over the first main surface of the encapsulation body. At least one trace of the at least one of the metal layer and the organic layer is removed by laser ablation. The encapsulation body is then separated into a plurality of semiconductor device packages along the at least one trace.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device package, the method comprising:
encapsulating at least partially a plurality of semiconductor chips with encapsulating material to form an encapsulation body, the encapsulation body having a first main surface and a second main surface;
forming at least one of a metal layer and an organic layer over the first main surface of the encapsulation body;
removing at least one trace of the at least one of the metal layer and the organic layer by laser ablation; and then
separating the encapsulation body into a plurality of semiconductor device packages along the at least one trace by mechanical sawing, wherein the encapsulation body comprises a first zone comprising encapsulating material and a second zone comprising a semiconductor material of a semiconductor chip, wherein the at least one of the metal layer and the organic layer extends over the first zone and the second zone, and the at least one trace extends over the first zone and the second zone, wherein separating the encapsulation body cuts through encapsulating material of the first zone and cuts through semiconductor material of the second zone.

2. The method of claim 1 , wherein the first zone and the second zone are arranged side-by-side in relation to the plate-like form.

3. The method of claim 1 , wherein the first zone and the second zone are arranged one over the other in relation to the plate-like form.

4. The method of claim 1 , further comprising:
forming a first dielectric layer extending over the at least one of the metal layer and the organic layer prior to laser ablation.

5. The method of claim 1 , further comprising:
forming a second dielectric layer extending over the first main surface of the encapsulation body and beneath the at least one of the metal layer and the organic layer prior to laser ablation.

6. The method of claim 1 , further comprising:
removing at least two parallel traces of the at least one of the metal layer and the organic layer by laser ablation, wherein the encapsulation body is separated along the at least two parallel traces.

7. The method of claim 1 , further comprising:
labeling the semiconductor device package by laser marking in the same laser work station used for the laser ablation,
wherein the labeling comprises scribing at least one of letters, characters and numbers into at least one of the metal layer and the organic layer.

8. The method of claim 7 , wherein the laser marking is performed prior to separating the encapsulation body.

9. The method of claim 1 , further comprising:
forming an electrical redistribution structure over the second main surface of the encapsulation body.

10. The method of claim 9 , further comprising:
dividing the electrical redistribution structure when separating the encapsulation body along the at least one trace.

11. The method of claim 1 , wherein the semiconductor chips have chip electrodes facing away from the first main surface.

12. A method of laser machining a layer stack comprising an encapsulation body containing a plurality of semiconductor chips, the method comprising:
labeling semiconductor device packages to be separated out of the layer stack by laser marking, wherein the laser marking comprises scribing at least one of letters, characters and numbers into at least one of a metal layer and an organic layer; and
removing at least one trace of at least one of a metal layer and an organic layer covering the encapsulation body by laser ablation, wherein the at least one trace corresponds to an encapsulation body separation line for semiconductor device package separation,
wherein the laser marking and the laser ablation for semiconductor device package separation are performed by using the same laser equipment.

13. A method of manufacturing a semiconductor device package, the method comprising:
encapsulating at least partially a plurality of semiconductor chips with encapsulating material to form an encapsulation body, the encapsulation body having a plate-like form with a first main surface and a second main surface;
forming a metal layer over the first main surface of the encapsulation body;
forming an electrical redistribution structure over the second main surface of the encapsulation body, wherein chip electrodes of the semiconductor chips face the electrical redistribution structure and are electrically connected to the electrical redistribution structure;
removing at least one trace of the metal layer by laser ablation; and
separating the encapsulation body into a plurality of semiconductor device packages along the at least one trace by removing at least one of the encapsulating material and a semiconductor material of the semiconductor chip after the removing at least one trace of the metal layer.

14. The method of claim 13 , wherein the encapsulation body is separated by mechanical sawing.

Assignees

• Infineon Technologies Ag

Inventors

• Wachter Ulrich
• Wagner Eva
• Beer Gottfried

Classifications

• H10W42/276

  the arrangements being on an external surface of the package, e.g. on the outer surface of an encapsulation · CPC title

• H10W44/248

  for antennas · CPC title

• H10W46/401

  for identification or tracking · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W70/09

  extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs · CPC title