Semiconductor structure including a layer of a first metal between a diffusion barrier layer and a second metal and method for the formation thereof

US9620453B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9620453-B2
Application numberUS-201414512850-A
CountryUS
Kind codeB2
Filing dateOct 13, 2014
Priority dateOct 13, 2014
Publication dateApr 11, 2017
Grant dateApr 11, 2017

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A method includes providing a semiconductor structure including a recess. The recess includes at least one of a contact via and a trench. A layer of a first metal is deposited over the semiconductor structure. An electroless deposition process is performed. The electroless deposition process removes a first portion of the layer of first metal from the semiconductor structure and deposits a first layer of a second metal over the semiconductor structure. An electroplating process is performed. The electroplating process deposits a second layer of the second metal over the first layer of second metal. A second portion of the layer of first metal remains in the semiconductor structure.

First claim

Opening claim text (preview).

What is claimed: 1. A method, comprising: providing a semiconductor structure comprising a recess, said recess comprising at least one of a contact via and a trench; depositing a layer of a first metal over said semiconductor structure, said layer of a first metal having a passivation layer comprising an oxide of said first metal disposed thereon; performing an electroless deposition process, said electroless deposition process removing said passivation layer, removing a first portion of said layer of said first metal from said semiconductor structure, and depositing a first layer of a second metal over said semiconductor structure; and performing an electroplating process, said electroplating process depositing a second layer of said second metal over said first layer of said second metal; wherein a second portion of said layer of said first metal remains in said semiconductor structure. 2. The method of claim 1 , further comprising bringing said semiconductor structure into contact with an electrolyte comprising ions of said second metal, said electroless deposition process being performed while said semiconductor structure is in contact with said electrolyte. 3. The method of claim 2 , wherein said electroplating process is performed while said semiconductor structure is in contact with said electrolyte and wherein performing said electroplating process comprises applying at least one of a voltage and a current between said semiconductor structure and an electrode contacting said electrolyte. 4. The method of claim 3 , wherein said at least one of a voltage and a current is applied between said semiconductor structure and said electrode upon expiry of a predetermined time after bringing said semiconductor structure into contact with said electrolyte. 5. The method of claim 3 , wherein said at least one of a voltage and a current is applied between said semiconductor structure upon detection of a change of a reflection of light from said semiconductor structure. 6. The method of claim 3 , wherein said electroless deposition process is stopped by applying said at least one of a voltage and a current between said semiconductor structure and said electrode. 7. The method of claim 3 , wherein a redox potential of said first metal in said electrolyte is smaller than a redox potential of said second metal in said electrolyte. 8. The method of claim 7 , wherein said first metal comprises cobalt and said second metal comprises at least one of copper, silver, gold, platinum and/or nickel. 9. The method of claim 8 , wherein said first metal further comprises a dopant. 10. The method of claim 9 , wherein said dopant comprises nitrogen. 11. The method of claim 9 , wherein said deposition of said layer of first metal comprises forming a stop sublayer for said electroless deposition process in said layer of said first metal, a concentration of said dopant in said stop sublayer being greater than a concentration of said dopant in a portion of said layer of said first metal above said stop sublayer. 12. The method of claim 10 , wherein said electrolyte comprises a solution of sulfuric acid and copper sulfate pentahydrate. 13. The method of claim 12 , wherein said deposition of said layer of said first metal comprises performing at least one of a chemical vapor deposition process and an atomic layer deposition process. 14. The method of claim 13 , wherein said deposition of said layer of said first metal comprises performing a substantially conformal chemical vapor deposition process. 15. The method of claim 13 , further comprising, before depositing said layer of said first metal over said semiconductor structure, depositing a diffusion barrier layer over said semiconductor structure, said diffusion barrier layer being adapted to substantially prevent a diffusion of said second metal through said diffusion barrier layer. 16. The method of claim 15 , wherein said diffusion barrier layer comprises tantalum nitride. 17. The method of claim 16 , wherein said layer of said first metal has a thickness in at least one of a range from about 1-100 nm and a range from about 5-40 nm. 18. The method of claim 13 , wherein said deposition of said layer of said first metal comprises a chemical vapor deposition process, and wherein: a flow of a process gas comprising a precursor and a carrier gas is in a range from about 50-4000 sccm; a deposition temperature is in a range from about 100-300° C.; and a pressure of said process gas is in a range from about 2-40 Torr. 19. The method of claim 14 , wherein: a flow of a process gas comprising a precursor and a carrier gas is in a range from about 300-1000 sccm; a deposition temperature is in a range from about 125-225° C.; and a pressure of said process gas is in a range from about 5-15 Torr. 20. A method, comprising: providing a semiconductor structure comprising a recess, said recess comprising at least one of a contact via and a trench; depositing a layer of cobalt over said semiconductor structure, said layer of cobalt having a passivation layer comprising cobalt oxide disposed thereon; performing an electroless deposition process in the presence of an electrolyte comprising ions of said second metal, said electroless deposition process removing said passivation layer, removing a first portion of said layer of cobalt from said semiconductor structure, and depositing a first layer of a second metal over said semiconductor structure, wherein a redox potential of cobalt in said electrolyte is smaller than a redox potential of said second metal in said electrolyte; and performing an electroplating process, said electroplating process depositing a second layer of said second metal over said first layer of said second metal; wherein a second portion of said layer of said first metal remains in said semiconductor structure. 21. The method of claim 20 , wherein said second metal comprises at least one of copper, silver, gold, platinum and/or nickel. 22. The method of claim 20 , wherein said layer of cobalt further comprises a dopant. 23. The method of claim 22 , wherein said dopant comprises nitrogen. 24. The method of claim 22 , wherein said deposition of said layer of cobalt comprises forming a stop sublayer for said electroless deposition process in said layer of cobalt using said dopant, a concentration of said dopant in said stop sublayer being greater than a concentration of said dopant in a portion of said layer of cobalt above said stop sublayer.

Assignees

Inventors

Classifications

  • Electrolytic deposition, i.e. electroplating; Electroless plating · CPC title

  • using a liquid · CPC title

  • Chemical deposition, e.g. chemical vapour deposition [CVD] · CPC title

  • by filling conductive material into holes, grooves or trenches · CPC title

  • H10W20/044Primary

    for electroless plating · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US9620453B2 cover?
A method includes providing a semiconductor structure including a recess. The recess includes at least one of a contact via and a trench. A layer of a first metal is deposited over the semiconductor structure. An electroless deposition process is performed. The electroless deposition process removes a first portion of the layer of first metal from the semiconductor structure and deposits a firs…
Who is the assignee on this patent?
Globalfoundries Inc
What technology area does this patent fall under?
Primary CPC classification H10W20/044. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Apr 11 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).