Stacked microelectronic assembly with TSVS formed in stages and carrier above chip

Patent metadata

Field	Value
Publication number	US-9620437-B2
Application number	US-201615047295-A
Country	US
Kind code	B2
Filing date	Feb 18, 2016
Priority date	Dec 2, 2010
Publication date	Apr 11, 2017
Grant date	Apr 11, 2017

Abstract

A microelectronic assembly is provided which includes a first element consisting essentially of at least one of semiconductor or inorganic dielectric material having a surface facing and attached to a major surface of a microelectronic element at which a plurality of conductive pads are exposed, the microelectronic element having active semiconductor devices therein. A first opening extends from an exposed surface of the first element towards the surface attached to the microelectronic element, and a second opening extends from the first opening to a first one of the conductive pads, wherein where the first and second openings meet, interior surfaces of the first and second openings extend at different angles relative to the major surface of the microelectronic element. A conductive element extends within the first and second openings and contacts the at least one conductive pad.

First claim

The invention claimed is:

1. A microelectronic assembly, comprising:
a first element consisting essentially of at least one of semiconductor or inorganic dielectric material;
a microelectronic element attached to the first element such that a surface of the first element faces a major surface of the microelectronic element, the microelectronic element having a plurality of conductive pads exposed at the major surface and each having an upper surface facing toward the first element, the microelectronic element having active semiconductor devices therein;
a first opening extending from an exposed surface of the first element towards the surface thereof which faces the microelectronic element, and a second opening extending from the first opening to a first one of the conductive pads, wherein where the first and second openings meet, interior surfaces of the first and second openings extend at different angles relative to the major surface of the microelectronic element; and
a conductive element extending within the first and second openings and contacting the first one of the conductive pads, wherein the conductive element is directly bonded to the upper surface of the first one of the conductive pads.

2. A method of forming a microelectronic assembly, comprising:
(a) attaching a first element consisting essentially of at least one of semiconductor or inorganic dielectric material with a microelectronic element such that a first surface of the first element faces a major surface of the microelectronic element, the microelectronic element having at least one electrically conductive pad having an upper surface exposed at the major surface, the microelectronic element having active semiconductor devices adjacent the major surface;
(b) then forming a first conductive element extending through the first element, wherein the forming of the first conductive element includes directly bonding the first conductive element to the upper surface of the at least one conductive pad; and
(c) before or after step (b), forming a second conductive element extending through the microelectronic element, wherein the forming of the second conductive element includes directly bonding the second conductive element to the at least one conductive pad or a second conductive pad at the major surface.

3. The method as claimed in claim 2 , wherein the direct bonding of the first conductive element to the at least one conductive pad is performed without the use of solder.

4. The method as claimed in claim 2 , wherein the direct bonding of the second conductive element to the at least one conductive pad or the second conductive pad is performed without the use of solder.

5. The method as claimed in claim 2 , wherein the first and second conductive elements are exposed at opposite faces of the microelectronic assembly.

6. The method as claimed in claim 2 , wherein the microelectronic element includes a plurality of chips attached together at dicing lines, the method further comprising severing the microelectronic assembly along the dicing lanes into individual units, each unit including at least one of the plurality of chips.

7. The method as claimed in claim 6 , wherein the first element is a carrier which does not have active semiconductor devices therein.

8. The method as claimed in claim 7 , wherein the first element further includes at least one passive device therein.

9. The method as claimed in claim 7 , wherein the carrier mechanically supports the microelectronic element.

10. The method as claimed in claim 2 , wherein the step of forming the first conductive element includes forming an opening extending through the thickness of the first element after the step of attaching, and then depositing a metal layer at least within the opening in the first element, the metal layer contacting the upper surface of the at least one conductive pad exposed within the opening.

11. The method as claimed in claim 2 , wherein the step of forming the second conductive element includes forming an opening extending through the thickness of the microelectronic element after the step of attaching, and then depositing a metal layer at least within the opening, the metal layer contacting the lower surface of the at least one conductive pad exposed within the opening in the microelectronic element.

12. A method of forming a microelectronic assembly, comprising:
(a) attaching a first element consisting essentially of at least one of semiconductor or inorganic dielectric material with a microelectronic element such that a first surface of the first element faces a major surface of the microelectronic element, the microelectronic element having at least one electrically conductive pad having an upper surface exposed at the major surface, the microelectronic element having active semiconductor devices adjacent the major surface, wherein the first surface and the major surface each are defined by a dielectric material, and the attaching includes directly bonding the dielectric material of the first surface to the dielectric material of the major surface;
(b) then forming a first conductive element extending through the first element and contacting the upper surface of the at least one conductive pad; and
(c) before or after step (b), forming a second conductive element extending through the microelectronic element, the second conductive element contacting the at least one conductive pad or a second conductive pad at the major surface.

13. The method as claimed in claim 12 , wherein the forming of the first conductive element includes directly bonding the first conductive element to the upper surface of the at least one conductive pad, and the forming of the second conductive element includes directly bonding the second conductive element to the at least one conductive pad or the second conductive pad at the major surface.

14. The method as claimed in claim 13 , wherein the direct bonding of the first conductive element to the at least one conductive pad is performed without the use of solder.

15. The method as claimed in claim 13 , wherein the direct bonding of the second conductive element to the at least one conductive pad or the second conductive pad is performed without the use of solder.

16. The microelectronic assembly as claimed in claim 1 , wherein the conductive element is directly bonded to the upper surface of the first one of the conductive pads without the use of solder.

17. The microelectronic assembly as claimed in claim 1 , wherein the first surface and the major surface each are defined by a dielectric material, and the dielectric material of the first surface is directly bonded to the dielectric material of the major surface.

18. The microelectronic assembly as claimed in claim 1 , wherein the conductive element has at least one of cylindrical or frusto-conical shape.

19. The microelectronic assembly as claimed in claim 18 , wherein a first portion of the conductive element tapers uniformly from a first width adjacent the exposed surface of the first element to a second width at a first location within the second opening, and a second portion of the conductive element tapers uniformly from a third width adjacent the rear surface of the microelectronic element to a fourth width at the first location.

20. The microelectronic assembly as claimed in claim 1 , wherein the conductive element has a shape determined independently from a contour of an interior surface of at least one of the first and second openings.

Assignees

• Tessera Inc

Inventors

• Oganesian Vage
• Haba Belgacem
• Mohammed Ilyas
• Mitchell Craig
• Savalia Piyush

Classifications

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/942

  relative to underlying supporting features, e.g. bond pads, RDLs or vias · CPC title

• H10W72/251

  Materials · CPC title