Methods for fabricating integrated circuits with improved active regions

Patent metadata

Field	Value
Publication number	US-9620418-B2
Application number	US-201414538850-A
Country	US
Kind code	B2
Filing date	Nov 12, 2014
Priority date	Nov 12, 2014
Publication date	Apr 11, 2017
Grant date	Apr 11, 2017

Abstract

Methods for fabricating integrated circuits having improved active regions are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate having an upper surface and including active regions and isolation regions formed in a low voltage device area and in a high voltage device area. The method includes selectively forming voids between the isolation regions and the active regions in the high voltage device area to expose active side surfaces. The method further includes oxidizing the upper surface and the active side surfaces to form a gate oxide layer over the low voltage device area and the high voltage device area.

First claim

What is claimed is:

1. A method for fabricating an integrated circuit, the method comprising:
providing a semiconductor substrate having an upper surface and including active regions and isolation regions formed in a low voltage device area and in a high voltage device area, wherein the isolation regions are formed with an upper surface at a step height over the active regions, and wherein the isolation regions have sidewalls in contact with the active regions;
selectively etching the upper surface of the isolation regions to reduce the step height and selectively etching the sidewalls of the isolation regions to form voids between the isolation regions and the active regions in the high voltage device area to expose active side surfaces; and
oxidizing the upper surface and the active side surfaces to form a gate oxide layer over the low voltage device area and the high voltage device area.

2. The method of claim 1 wherein selectively etching the upper surface of the isolation regions to reduce the step height and selectively etching the sidewalls of the isolation regions to form voids between the isolation regions and the active regions in the high voltage device area comprises masking the low voltage device area while etching the high voltage device area.

3. The method of claim 1 wherein selectively etching the sidewalls of the isolation regions to form the voids comprises forming the voids with a void depth from about 150 Å to about 200 Å below the upper surface of the isolation region.

4. The method of claim 1 further comprising forming doped regions in the high voltage device area and forming doped regions in the low voltage device area, wherein:
forming the doped regions in the high voltage device area comprises:
forming a sacrificial layer over the high voltage device area and over the low voltage device area;
forming a first mask over the sacrificial layer covering the low voltage device area and partially covering the high voltage device area to define first exposed portions of the high voltage device area;
forming the doped regions in the first exposed portions;
etching the first exposed portions of the high voltage device area, wherein etching the first exposed portions of the high voltage device area comprises selectively etching the upper surface of the isolation regions to reduce the step height and selectively etching the sidewalls of the isolation regions to form voids between the isolation regions and the active regions in the first exposed portions of the high voltage device area to expose active side surfaces;
removing the first mask;
forming a second mask covering the low voltage device area and partially covering the high voltage device area to define second exposed portions of the high voltage device area;
forming the doped regions in the second exposed portions;
etching the second exposed portions of the high voltage device area, wherein etching the second exposed portions of the high voltage device area comprises selectively etching the upper surface of the isolation regions to reduce the step height and selectively etching the sidewalls of the isolation regions to form voids between the isolation regions and the active regions in the second exposed portions of the high voltage device area to expose active side surfaces; and
removing the second mask; and

forming the doped regions in the low voltage device area comprises:
forming a third mask partially covering the low voltage device area and covering the high voltage device area to define third exposed portions of the low voltage device area;
forming the doped regions in the third exposed portions;
removing the third mask;
forming a fourth mask partially covering the low voltage device area and covering the high voltage device area to define fourth exposed portions of the low voltage device area;
forming the doped regions in the fourth exposed portions; and

removing the fourth mask.

5. The method of claim 1 wherein selectively etching the upper surface of the isolation regions to reduce the step height comprises eliminating the step height between the upper surface of the semiconductor substrate and the upper surface of the isolation regions.

6. The method of claim 1 wherein selectively etching the upper surface of the isolation regions to reduce the step height and selectively etching the sidewalls of the isolation regions to form voids between the isolation regions and the active regions in the high voltage device area to expose the active side surfaces comprises:
forming a first mask covering the low voltage device area and partially covering the high voltage device area to define first exposed portions of the high voltage device area;
etching first voids into the isolation regions in the first exposed portions;
forming the doped regions in the first exposed portions;
removing the first mask;
forming a second mask covering the low voltage device area and partially covering the high voltage device area to define second exposed portions of the high voltage device area;
forming the doped regions in the second exposed portions;
etching second voids into the isolation regions in the second exposed portions; and
removing the second mask.

7. The method of claim 1 wherein the upper surface of the semiconductor substrate in the active regions is not etched while selectively etching the upper surface of the isolation regions to reduce the step height and selectively etching the sidewalls of the isolation regions to form voids between the isolation regions and the active regions in the high voltage device area to expose active side surfaces.

8. The method of claim 1 wherein selectively etching the upper surface of the isolation regions to reduce the step height and selectively etching the sidewalls of the isolation regions to form voids between the isolation regions and the active regions in the high voltage device area to expose the active side surfaces comprises:
forming a first mask covering the low voltage device area and partially covering the high voltage device area to define first exposed portions of the high voltage device area;
etching first voids into the isolation regions in the first exposed portions;
removing the first mask;
forming a first cap screen oxide layer on the semiconductor substrate after removing the first mask; and
removing residue from the semiconductor substrate after forming the first cap screen oxide layer.

9. The method of claim 1 further comprising:
masking the high voltage device area; and
forming doped regions in the low voltage device area before oxidizing the upper surface and the active side surfaces to form the gate oxide layer over the low voltage device area and the high voltage device area.

10. The method of claim 1 further comprising forming a sacrificial layer overlying the semiconductor substrate, wherein selectively etching the upper surface of the isolation regions to reduce the step height and selectively etching the sidewalls of the isolation regions to form the voids between the isolation regions and the active regions in the high voltage device area to expose the active side surfaces comprises:
forming a first mask covering the low voltage device area and partially covering the high voltage device area to define first exposed portions of the high voltage device area;
etching into the sacrificial layer overlying the first exposed portions to form first recessed sacrificial layer portions;
removing the first mask;
forming a second mask covering the low voltage device area and partially covering the high voltage device area to define second exposed portions of the high voltage device area;
etching into the sacrificial layer overlying the secon

Assignees

• Globalfoundries Sg Pte Ltd

Inventors

• Li Liang
• Lu Wei
• Goh Lian Choo
• Chong Yung Fu Alfred
• Liu Fangyue
• See Alex

Classifications

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/22

  using masks · CPC title

• H10P30/21

  of electrically active species · CPC title

• H10D84/0151

  Manufacturing their isolation regions · CPC title

• H10D84/0156

  Manufacturing their doped wells · CPC title