Production method

Patent metadata

Field	Value
Publication number	US-9620375-B2
Application number	US-201514669072-A
Country	US
Kind code	B2
Filing date	Mar 26, 2015
Priority date	Sep 28, 2012
Publication date	Apr 11, 2017
Grant date	Apr 11, 2017

Abstract

A production methods includes providing a substrate including a lattice plane that extends in a non-symmetrical manner and such that it is offset at an angle α from at least a first or second main surface region of the substrate, the first and second main surface regions extending parallel to each other; anisotropic etching, starting from the first main surface region, into the substrate so as to obtain an etching structure which includes, in a plane extending perpendicularly to the first main surface region, two different etching angles relative to the first main surface region; arranging a cover layer on the first main surface region, so that the cover layer lies against the etching structure in at least some sections; and removing, section-by-section, the material of the substrate starting from the second main surface region in the area of the deformed cover layer, so that the cover layer is exposed in at least one window region.

First claim

The invention claimed is:

1. A production method comprising:
providing a semiconductor substrate comprising a lattice plane that extends in a non-symmetrical manner and such that it is offset at an angle α from at least a first main surface region or a second main surface region of the semiconductor substrate, the first main surface region and the second main surface region extending parallel to each other;
starting from the first main surface region, section-by-section anisotropic etching into the semiconductor substrate so as to achieve an etching structure which comprises, in a plane extending perpendicularly to the first main surface region of the semiconductor substrate, two different etching angles relative to the first main surface region;
arranging a cover layer on the first main surface region of the semiconductor substrate, so that the cover layer is deformed to lie against the etching structure in at least some sections; and
removing, section-by-section, the material of the semiconductor substrate starting from the second main surface region in the area of the deformed cover layer, so that the cover layer is exposed in at least one window region.

2. The production method as claimed in claim 1 , wherein the lattice plane of the semiconductor substrate is the (100) lattice plane.

3. The production method as claimed in claim 1 , wherein the angle α ranges from 1° to 40°.

4. The production method as claimed in claim 1 , wherein providing the semiconductor substrate comprises cutting out the semiconductor substrate from a semiconductor ingot at the angle α, said semiconductor ingot comprising a (100) standard lattice orientation.

5. The production method as claimed in claim 1 , further comprising:
structured application of a mask onto the first main surface region of the semiconductor substrate, said first main surface region being exposed in an etching region, and edges of the etching region extending parallel to <110> directions of a lattice structure of the semiconductor substrate;
said anisotropic etching being performed starting from the first main surface region into the semiconductor substrate within the etching region.

6. The production method as claimed in claim 1 , wherein the two etching angles that differ relative to the first main surface region are located between the first main surface region and one {111} lattice plane of the semiconductor substrate, respectively.

7. The production method as claimed in claim 1 , wherein arranging the cover layer on the first main surface region of the semiconductor substrate comprises sputter deposition or vapor deposition of the cover layer onto the first main surface region of the semiconductor substrate.

8. The production method as claimed in claim 1 , wherein arranging the cover layer on the first main surface region of the semiconductor substrate comprises:
applying the cover layer onto the first main surface region of the semiconductor substrate, so that the cover layer extends across the etching structure; and
deforming the cover layer in the area of the etching structure, so that cover layer lies against the etching structure in at least some sections.

9. The production method as claimed in claim 8 , wherein said application of the cover layer is performed under a first pressure, so that the first pressure exists between the cover layer and the etching structure; and
wherein said deformation of the cover layer in the area of the etching structure is performed under a second pressure larger than the first pressure, and at a temperature higher than a softening point of the cover layer, so that the cover layer will deform in the area of the etching structure due to a pressure difference between the first pressure and the second pressure, so that the cover layer lies against the etching structure in at least some sections.

10. The production method as claimed in claim 8 , wherein said anisotropic etching is performed starting from the first main surface region into the semiconductor substrate to the second main surface region, so that the etching structure will extend from the first main surface region to the second main surface region,
wherein in the deformation of the cover layer in the area of the etching structure, a first pressure is provided adjacently to the cover layer, and a second pressure larger than the first pressure is provided adjacently to the second main surface region, said deformation of the cover layer in the area of the etching structure being performed at a temperature higher than a softening point of the cover layer, so that the cover layer will deform in the area of the etching structure due to a pressure difference between the first pressure and the second pressure, so that the cover layer lies against the etching structure in at least some sections.

11. The production method as claimed in claim 1 , wherein said arranging of the cover layer comprises bonding.

12. The production method as claimed in claim 1 , wherein the cover layer is optically transparent at least in the window region.

13. The production method as claimed in claim 1 , wherein the cover layer comprises glass.

14. The production method as claimed in claim 1 , further comprising:
providing a device semiconductor substrate comprising a microscanner mirror, which in its idle position is arranged in parallel with a surface region of the device semiconductor substrate;
bonding the cover layer outside the area of the deformed cover layer onto the surface region of the device semiconductor substrate, so that the window region is arranged adjacently to the microscanner mirror.

15. A production method comprising:
providing a semiconductor substrate comprising a (100) lattice plane that extends in a non-symmetrical manner and such that it is offset at an angle a from at least a first main surface region or a second main surface region of the semiconductor substrate, the first main surface region and the second main surface region extending parallel to each other;
starting from the first main surface region, section-by-section anisotropic etching into the semiconductor substrate so as to achieve an etching structure which comprises, in a plane extending perpendicularly to the first main surface region of the semiconductor substrate, two different etching angles relative to the first main surface region;
arranging a cover layer on the first main surface region of the semiconductor substrate, so that the cover layer is deformed to lie against the etching structure in at least some sections; and
removing, section-by-section, the material of the semiconductor substrate starting from the second main surface region in the area of the deformed cover layer, so that in the semiconductor substrate a window region is formed wherein the cover layer is arranged in a manner that is non-parallel to the first main surface region and wherein the cover layer is exposed.

Assignees

• Fraunhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung E V

Inventors

• Langa Sergiu
• Drabe Christian
• Sandner Thilo

Classifications

• H10P50/242 Primary

  of Group IV materials · CPC title

• H01L21/3065 Primary

  Electricity · mapped topic

• G02B26/0833

  the reflecting element being a micromechanical device, e.g. a MEMS mirror, DMD (G02B26/0825 takes precedence; micromechanical devices in general B81B) · CPC title

• B81C1/00317 Primary

  Packaging optical devices · CPC title