Fabrication of semiconductor junctions

Patent metadata

Field	Value
Publication number	US-9620360-B1
Application number	US-201514953117-A
Country	US
Kind code	B1
Filing date	Nov 27, 2015
Priority date	Nov 27, 2015
Publication date	Apr 11, 2017
Grant date	Apr 11, 2017

Abstract

A method comprises providing a cavity structure on the substrate comprising a first growth channel extending in a first direction, a second growth channel extending in a second direction, wherein the second direction is different from the first direction and the second channel is connected to the first channel at a channel junction, a first seed surface in the first channel, at least one opening for supplying precursor materials to the cavity structure, selectively growing from the first seed surface a first semiconductor structure substantially only in the first direction and in the first channel, thereby forming a second seed surface for a second semiconductor structure at the channel junction, growing in the second channel the second semiconductor structure in the second direction from the second seed surface, thereby forming the semiconductor junction comprising the first and the second semiconductor structure.

First claim

What is claimed is:

1. A method for fabricating a semiconductor junction on a substrate, the method comprising:
providing a cavity structure on the substrate, the cavity structure comprising:
a first growth channel extending in a first direction;
a second growth channel extending in a second direction, wherein the second direction is different from the first direction and the second channel is connected to the first channel at a channel junction;
a first seed surface in the first channel;
at least one opening for supplying precursor materials to the cavity structure;
selectively growing from the first seed surface a first semiconductor structure substantially only in the first direction and in the first channel, thereby forming a second seed surface for a second semiconductor structure at the channel junction;
growing in the second channel the second semiconductor structure in the second direction from the second seed surface, thereby forming the semiconductor junction comprising the first and the second semiconductor structure, wherein the growing of the first and the second semiconductor structure is performed by vapor phase epitaxy, and the crystal orientation of the first seed surface and one or more parameters of the vapor phase epitaxy are adapted to grow the first semiconductor structure anisotropically in the first direction only.

2. A method as claimed in claim 1 , wherein the crystal orientation of the second seed surface and one or more parameters of the vapor phase epitaxy are adapted to grow the second semiconductor structure in the second direction.

3. A method as claimed in claim 1 , wherein the growing of the first and the second semiconductor structure is performed by one of: metalorganic chemical vapor deposition (MOCVD) and hydride vapor phase epitaxy.

4. A method as claimed in claim 1 , wherein the first direction and the second direction are substantially perpendicular to each other.

5. A method as claimed in claim 1 , wherein the cavity structure comprises a plurality of second growth channels, wherein the plurality of second growth channels are arranged in parallel to each other and substantially perpendicular to the first channel.

6. A method as claimed in claim 5 , comprising:
growing a plurality of second semiconductor structures simultaneously in the plurality of second growth channels, thereby forming simultaneously a plurality of semiconductor junctions.

7. A method as claimed in claim 5 , wherein the cavity structure comprises one or more pairs of second growth channels, each pair comprising a first arm and a second arm, wherein the first arm and the second arm extend from a channel junction in opposite directions, the method comprising:
growing simultaneously second semiconductor structures in the first arm and the second arm of the one or more pairs of second growth channels, thereby forming simultaneously one or more double semiconductor junctions.

8. A method as claimed in claim 7 , the method comprising fabricating a transistor from the first and the second semiconductor structures, wherein the first semiconductor structure forms the basis for one or more gate channel structures of the transistor, the second semiconductor structure of the first arm forms the basis for a drain structure of the transistor and the second semiconductor structure of the second arm forms the basis for a source structure of the transistor.

9. A method as claimed in claim 1 , wherein each of the first and the second semiconductor structures comprises a compound semiconductor material.

10. A method as claimed in claim 1 , wherein the first and the second semiconductor structures comprise the same compound semiconductor material, the compound semiconductor material of the first semiconductor structure is doped with a first dopant concentration and the compound semiconductor material of the second semiconductor structure is doped with a second dopant concentration, the first dopant concentration is dissimilar to the second dopant concentration.

11. A method as claimed in claim 1 , wherein the first and the second semiconductor structures comprise different compound semiconductor materials.

12. A method as claimed in claim 1 , wherein the first seed surface has an area of order 10 4 nm2 or less.

13. A method as claimed in claim 1 , wherein the first seed surface is a monocrystalline semiconductor surface.

14. A method as claimed in claim 1 , wherein the first seed surface comprises silicon.

15. A method as claimed in claim 1 , wherein the substrate is used as first seed surface.

16. A method as claimed in claim 1 , comprising, after growing the first and the second semiconductor structure, removing the cavity structure.

17. A method as claimed in claim 1 , comprising:
forming by selective etching a fin structure from the semiconductor junction, the fin structure comprising a plurality of parallel fins.

18. A method as claimed in claim 1 , wherein the first growth channel and the second growth channel extend laterally over the substrate.

19. A method as claimed in claim 1 , wherein the first growth channel extends vertically to the surface of the substrate and the second growth channel extends laterally over the surface of the substrate.

Assignees

• IBM

Inventors

• Borg Mattias B
• Moselund Kirsten E
• Riel Heike E
• Schmid Heinz

Classifications

• H10P14/3221

  Arsenides · CPC title

• H10P50/642

  Chemical etching · CPC title

• H10P14/3422

  Antimonides · CPC title

• H10P14/3421

  Arsenides · CPC title

• H10P14/2905

  Silicon, silicon germanium or germanium · CPC title