Low frequency converters having electrochemical capacitors

Patent metadata

Field	Value
Publication number	US-9620296-B2
Application number	US-201313853960-A
Country	US
Kind code	B2
Filing date	Mar 29, 2013
Priority date	Mar 30, 2012
Publication date	Apr 11, 2017
Grant date	Apr 11, 2017

Abstract

In one embodiment of the invention, a low frequency converter is described that includes a first electrochemical capacitor to charge to an input voltage and a second electrochemical capacitor that is coupled to the first electrochemical capacitor. The second electrochemical capacitor is associated with an output voltage of the low frequency converter. Each electrochemical capacitor may have a capacitance of at least one millifarad (mF) and a switching frequency that is less than one kilohertz.

First claim

What is claimed is:

1. A circuit comprising:
a first electrochemical capacitor to charge to an input voltage when coupled to an input voltage source with a switch; and
a second electrochemical capacitor coupled to the first electrochemical capacitor, the second electrochemical capacitor is associated with an output voltage of the circuit, wherein each electrochemical capacitor is integrated monolithically with the circuit, wherein each electrochemical capacitor comprises a pair of porous semiconductor structures, each porous semiconductor structure containing an electrolyte loaded into a plurality of pores.

2. The circuit of claim 1 , wherein each electrochemical capacitor has a capacitance of at least one millifarad (mF).

3. The circuit of claim 1 , wherein each electrochemical capacitor has a switching frequency that is less than one kilohertz.

4. The circuit of claim 1 , wherein each electrochemical capacitor has a switching frequency that is less than one hundred hertz.

5. The circuit of claim 1 , wherein each electrochemical capacitor comprises
a solid or semi-solid electrolyte layer separating the pair of porous semiconductor structures and penetrating the pair of porous semiconductor structures, wherein each electrochemical capacitor has an ultra-low effective series resistance based on the pores being planar and shallow.

6. The circuit of claim 1 , wherein the output voltage is approximately equal to the input voltage multiplied by a fixed ratio.

7. The circuit of claim 6 , wherein the fixed ratio is chosen from the following ratios: 1/2, 2/3, and 1/3.

8. The circuit of claim 1 , wherein the circuit comprises a multi-phase converter.

9. The circuit of claim 1 , wherein the circuit comprises a multi-phase boost converter.

10. The circuit of claim 1 , wherein the parameters of each electrochemical capacitor are designed based on the requirements of the circuit with the parameters including voltage, effective series resistance, quality factor, and size.

11. The circuit of claim 1 , wherein the circuit comprises a voltage doubler circuit.

12. The circuit of claim 1 , wherein the circuit is incorporated within an electronic device, the circuit being associated with a microprocessor and a silicon substrate.

13. The circuit of claim 1 , wherein the circuit comprises a voltage inverter circuit.

14. A method of operating a switched capacitor circuit, comprising:
providing an input voltage to charge a first electrochemical capacitor and a second electrochemical capacitor when the second electrochemical capacitor is coupled in series to the first electrochemical capacitor; and
discharging the first and second electrochemical capacitors when the second electrochemical capacitor is coupled in parallel to the first electrochemical capacitor, wherein each electrochemical capacitor comprises a pair of porous semiconductor structures, each porous semiconductor structure containing an electrolyte loaded into a plurality of pores; and a solid or semi-solid electrolyte layer separating the pair of porous semiconductor structures and penetrating the pair of porous semiconductor structures, wherein each electrochemical capacitor has an ultra-low effective series resistance based on the pores being planar and shallow.

15. The method of claim 14 , wherein each electrochemical capacitor has a capacitance of at least one millifarad (mF).

16. The method of claim 14 , wherein each electrochemical capacitor has a switching frequency that is less than one kilohertz.

17. The method of claim 14 , wherein each electrochemical capacitor has a switching frequency that is less than one hundred hertz.

18. The method of claim 14 , wherein each electrochemical capacitor is associated with a silicon substrate.

19. The method of claim 14 , wherein the output voltage is approximately equal to the input voltage multiplied by a fixed ratio that is chosen from the following ratios: 1/2, 2/3, and 1/3.

Assignees

• Gardner Donald S
• Kumar Pavan
• Intel Corp

Inventors

• Gardner Donald S
• Kumar Pavan

Classifications

• G06F1/04

  Generating or distributing clock signals or signals derived directly therefrom · CPC title

• H01G11/56 Primary

  Solid electrolytes, e.g. gels; Additives therein · CPC title

• H01G11/08

  Structural combinations, e.g. assembly or connection, of hybrid or EDL capacitors with other electric components, at least one hybrid or EDL capacitor being the main component · CPC title

• H02J7/00

  Circuit arrangements for charging or discharging batteries or for supplying loads from batteries · CPC title

• H01G11/04 Primary

  Hybrid capacitors · CPC title