Operating method of memory system

Patent metadata

Field	Value
Publication number	US-9620246-B2
Application number	US-201514712656-A
Country	US
Kind code	B2
Filing date	May 14, 2015
Priority date	Dec 18, 2014
Publication date	Apr 11, 2017
Grant date	Apr 11, 2017

Abstract

Second data is generated by re-reading first data using a second read voltage when a first ECC decoding to first data using a first read voltage fails. Third data is generated by performing a second ECC decoding to the second data. An error-bit-number, which is a number of bits different between the second data and the third data, is obtained when the second ECC decoding fails. The process is repeated by changing the second read voltage until the error-bit-number is smaller than a predetermined threshold value. A third ECC decoding is performed to an optimal data that is the second data read using the second read voltage, with which the error-bit-number is smaller than the predetermined threshold value.

First claim

What is claimed is:

1. A read method of a semiconductor memory system including a nonvolatile memory device and a memory controller, the read method comprising:
a first step of performing a first ECC decoding to first data stored in the nonvolatile memory device, wherein the first data is read using a first read voltage;
a second step of generating second data by re-reading the first data using a second read voltage when the first ECC decoding fails;
a third step of generating third data by performing a second ECC decoding to the second data;
a fourth step of obtaining an error-bit-number, which is a number of bits different between the second data and the third data, when the second ECC decoding fails;
a fifth step of repeating the second to fourth steps by changing the second read voltage until the error-bit-number is smaller than a predetermined threshold value; and
a sixth step of
performing a third ECC decoding to an optimal data.

2. The read method of the semiconductor memory system of claim 1 , wherein the fourth step performs an exclusive OR operation to the second data and the third data to obtain the number of error bits.

3. The read method of the semiconductor memory system of claim 1 , wherein the fifth step repeats the second to fourth steps by changing the second read voltage by a fixed amount of voltage variation.

4. The read method of the semiconductor memory system of claim 1 , wherein the second ECC decoding is a hard decoding.

5. The read method of the semiconductor memory system of claim 1 , wherein the third ECC decoding is a soft decoding.

6. A read method of a semiconductor memory system including a nonvolatile memory device and a memory controller, the read method comprising:
a first step of performing a first ECC decoding to first data stored in the nonvolatile memory device, wherein the first data is read using a first read voltage;
a second step of generating second data by re-reading the first data using a second read voltage when the first ECC decoding fails;
a third step of generating third data by performing a second ECC decoding to the second data;
a fourth step of obtaining an error-bit-number, which is a number of bits different between the second data and the third data, when the second ECC decoding fails;
a fifth step of obtaining N sets of error-bit-numbers by repeating N times the second to fourth steps by changing the second read voltage; and
a sixth step of
performing a third ECC decoding to an optimal data that is the second data read using the second read voltage; with which the error-bit-number is a minimum among the N sets of error-bit-numbers.

7. The read method of the semiconductor memory system of claim 6 , wherein the fourth step obtains the error-bit-number through an exclusive OR operation to the second data and the third data.

8. The read method of the semiconductor memory system of claim 6 , wherein the fifth step repeats the second to fourth steps by changing the second read voltage by a fixed amount of voltage variation.

9. The read method of the semiconductor memory system of claim 6 , wherein the second ECC decoding is a hard decoding.

10. The read method of the semiconductor memory system of claim 6 , wherein the third ECC decoding is a soft decoding.

11. A read method of a semiconductor memory system including a nonvolatile memory device and a memory controller, the read method comprising:
a first step of performing a first ECC decoding to first data stored in the nonvolatile memory device, wherein the first data is read using a first read voltage;
a second step of generating second data by re-reading the first data using a second read voltage when the first ECC decoding fails;
a third step of generating third data by performing a second ECC decoding to the second data;
a fourth step of obtaining an error-bit-number, which is a number of bits different between the second data and the third data, when the second ECC decoding fails;
a fifth step of obtaining N sets of error-bit-numbers by repeating N times the second to fourth steps by changing the second read voltage until the error-bit-number is smaller than a predetermined threshold value; and
a sixth step of
performing a third ECC decoding to a first optimal data that is the second data read using the second read voltage, with which the error-bit-number is smaller than the predetermined threshold value before the repetition of the second to fourth steps reaches the N times.

12. The read method of the semiconductor memory system of claim 11 , wherein the third step obtains the error-bit-number through an exclusive OR operation to the second data and the third data.

13. The read method of the semiconductor memory system of claim 11 , wherein the fifth step repeats the second to fourth steps by changing the read voltage by a fixed amount of voltage variation.

14. The read method of the semiconductor memory system of claim 11 , further comprising the seventh step of performing the third ECC decoding to a second optimal data that is the second data read using the second read voltage, with which the error-bit-number is minimum among the N sets of error-bit-numbers, when any of the N sets of error-bit-numbers is not smaller than the predetermined threshold value after the repetition of the second to fourth steps reaches the N times.

15. The read method of the semiconductor memory system of claim 11 , wherein the second ECC decoding is a hard decoding.

16. The read method of the semiconductor memory system of claim 11 , wherein the third ECC decoding is a soft decoding.

Assignees

• Sk Hynix Inc

Inventors

• Lee Hyung-Min

Classifications

• G11C29/028

  with adaption or trimming of parameters · CPC title

• G06F11/1048

  using arrangements adapted for a specific error detection or correction feature · CPC title

• G11C29/52 Primary

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G11C29/021

  in voltage or current generators · CPC title

• G11C2029/5004

  Voltage · CPC title