Method of operating a NAND flash memory device

Patent metadata

Field	Value
Publication number	US-9620231-B2
Application number	US-201615065301-A
Country	US
Kind code	B2
Filing date	Mar 9, 2016
Priority date	Mar 13, 2013
Publication date	Apr 11, 2017
Grant date	Apr 11, 2017

Abstract

Serial NAND flash memory may be provided with the characteristics of continuous read of the memory across page boundaries and from logically contiguous memory locations without wait intervals, while also being clock-compatible with the high performance serial flash NOR (“HPSF-NOR”) memory read commands so that the serial NAND flash memory may be used with controllers designed for HPSF-NOR memory. Serial NAND flash memory having these compatibilities is referred to herein as high-performance serial flash NAND (“SPSF-NAND”) memory. Since devices and systems which use HPSF-NOR memories and controllers often have extreme space limitations, HPSF-NAND may also be provided with the same physical attributes of low pin count and small package size of HPSF-NOR memory for further compatibility. HPSF-NAND memory is particularly suitable for code shadow applications, even while enjoying the low “cost per bit” and low per bit power consumption of a NAND memory array at higher densities.

First claim

The invention claimed is:

1. A method of operating a NAND flash memory device comprising:
receiving a read command which corresponds to a high-performance serial flash NOR (“HPSF-NOR”) read command and is clock-compatible therewith; and
providing, from the NAND flash memory device in response to the read command receiving step, a continuous data output across page boundaries and from logically contiguous memory locations without wait intervals.

2. The method of claim 1 wherein the read command is one of a Read command 03h, a Fast Read command 0Bh, a Fast Read Dual Output command 3Bh, a Fast Read Quad Output command 6Bh, a Fast Read Dual I/O command BBh, or a Fast Read Quad I/O command EBh.

3. The method of claim 1 wherein the NAND flash memory device comprises a NAND flash memory array and a page buffer coupled to the NAND flash memory array, and wherein the providing step comprises:
reading a page of data from the NAND flash memory array to the page buffer;
ECC processing data in the page buffer to produce ECC processed data; and
outputting ECC processed data from the page buffer;
wherein time used for the page reading step and the ECC processing step is buried in time used for the data outputting step.

4. The method of claim 1 wherein the page reading step is performed using bad block management.

5. The method of claim 1 wherein the NAND flash memory device comprises a NAND flash memory array and a page buffer coupled to the NAND flash memory array, and further comprising:
selecting a page of the NAND flash memory array;
storing data from the selected page in the page buffer;
performing ECC computations on the data in the page buffer;
outputting the data from the page buffer; and
repeating the page selecting, data storing, ECC computation performing, and data outputting steps so that the continuous data output is provided;
wherein the page selecting step initially comprises selecting a default page in the NAND flash memory array, and subsequently comprises selecting successive sequential pages of the NAND flash memory array;
wherein the page selecting, data storing, and ECC computation performing steps are initially performed automatically during power-up of the flash memory, and are subsequently performed in response to the read command; and
wherein the data outputting step is performed in response to the read command.

6. The method of claim 1 further comprising:
selecting a default page of a NAND flash memory array of the NAND flash memory device during power-up thereof;
storing data from the default page of the NAND flash memory array in a page buffer during power-up of the NAND flash memory;
performing ECC computations on the data stored in the page buffer after the storing step; and
receiving the read command.

7. The method of claim 1 wherein the NAND flash memory device comprises a NAND flash memory array and a page buffer associated with the NAND flash memory array, further comprising:
setting the flash memory device in a continuous read mode or a buffer read mode;
transferring a page of data from a default page of the NAND flash memory array to the page buffer;
after the page data transferring step, receiving the read command; and
when the flash memory device is in the continuous read mode, outputting the continuous data output from the flash memory device in response to the read command receiving step.

8. The method of claim 7 further comprising:
ECC processing the default page of data in the page buffer to provide an ECC processed default page of data;
wherein the read command is received after the ECC processing step;
wherein when the flash memory is in the continuous read mode, outputting the continuous data beginning with the ECC processed default page of data in the page buffer.

9. The method of claim 8 further comprising establishing the default page under a manufacturer's control.

10. The method of claim 8 further comprising establishing the default page under a user's control.

11. A method of operating a memory having a NAND flash memory array and a page buffer coupled to the NAND flash memory array, comprising:
receiving a continuous read command comprising a command code and a starting address; and
providing, from the NAND flash memory array via the page buffer and in response to the read command receiving step, a continuous data output across page boundaries and from logically contiguous memory locations without wait intervals;
wherein the providing step begins with column 00 of the page buffer regardless of the starting address.

12. The method of claim 11 wherein the read command is one of a Read command 03h, a Fast Read command 0Bh, a Fast Read Dual Output command 3Bh, a Fast Read Quad Output command 6Bh, a Fast Read Dual I/O command BBh, or a Fast Read Quad I/O command EBh.

Assignees

• Winbond Electronics Corp

Inventors

• Jigour Robin John
• Chen Hui
• Michael Oron

Classifications

• G11C16/3404

  Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells · CPC title

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F11/1068 Primary

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title

• G11C16/20

  Initialising; Data preset; Chip identification · CPC title