Memory provided with associated volatile and non-volatile memory cells

Patent metadata

Field	Value
Publication number	US-9620212-B2
Application number	US-201515110710-A
Country	US
Kind code	B2
Filing date	Jan 7, 2015
Priority date	Jan 10, 2014
Publication date	Apr 11, 2017
Grant date	Apr 11, 2017

Abstract

A memory array including: a plurality of volatile memory cells, each including a latch; and a plurality of non-volatile memory cells, each including at least one resistive element that can be programmed by the direction of a current passed therethrough in order to take at least two resistive states, each of the non-volatile memory cells being associated with a corresponding cell from the volatile memory cells.

First claim

The invention claimed is:

1. A memory array comprising:
a plurality of volatile memory cells each comprising a latch;
a plurality of non-volatile memory cells each comprising at least one resistive element programmable by the direction of current passed through it to have one of at least two resistive states, wherein each of the non-volatile memory cells is associated with a corresponding one of said volatile memory cells; and
a read/write circuit coupled to each of the volatile and non-volatile memory cells via one or more pairs of bit lines, the read/write circuit having a comparator adapted to read a first data bit stored by a first of the volatile memory cells and to read a second data bit stored by a second of the non-volatile memory cells.

2. The memory array of claim 1 , wherein said read/write circuit is adapted to perform at least one of:
read the first data bit stored by a first of said volatile memory cells and program, based on said first data bit, the resistive state of a first of said non-volatile memory cells, associated with said first volatile memory cell; and
read, from a second of said non-volatile memory cells, a programmed resistive state representing the second data bit and write said second data bit to a second of said volatile memory cells associated with said second non-volatile memory cell.

3. The memory array of claim 1 , wherein said comparator has first and second inputs, and wherein said read/write circuit further comprises:
at least one multiplexer adapted to couple the first and second inputs of the comparator to complementary storage nodes of said first volatile memory cell to read said first data bit, and to couple the first and second inputs of the comparator to outputs of an amplifier adapted to detect the programmed resistive state of said second non-volatile memory cell.

4. The memory array of claim 1 , wherein said read/write circuit further comprises:
a write circuit adapted to write a data bit to a first of said volatile memory cells by applying a voltage across complementary storage nodes of said first volatile memory cell and to program a resistive state of a first of said non-volatile memory cells by passing a current through the resistive element of the first non-volatile memory cell.

5. The memory array of claim 1 , further comprising a plurality of selection lines, and wherein:
each of said volatile memory cells and its associated non-volatile memory cell are coupled to a same selection line of said memory array.

6. The memory array of claim 1 , wherein each of said volatile memory cells and its associated non-volatile memory cell are each coupled to a same pair of bit lines.

7. The memory array of claim 1 , wherein said volatile memory cells are each coupled to a first pair of bit lines and wherein said non-volatile memory cells are each coupled to a second pair of bit lines.

8. The memory array of claim 1 , wherein each of said volatile memory cells is coupled to a voltage supply rail coupled via a switch to a supply voltage level.

9. The memory array of claim 1 , wherein said non-volatile memory cells each comprise a single resistive element coupled in series with a first transistor between a pair of bit lines.

10. The memory array of claim 1 , wherein said non-volatile memory cells each comprise:
a first resistive element coupled in series with a first transistor between a first bit line and a first supply voltage; and
a second resistive element coupled in series with a second transistor between a second bit line and said first supply voltage.

11. The memory array of claim 1 , wherein said at least one resistive element of each of said non-volatile memory cells is one of:
a spin transfer torque element with in-plane anisotropy;
a spin transfer torque element with perpendicular-to-plane anisotropy; and
a reduction oxide element.

12. A method of data back-up in the memory array of claim 1 , the method comprising:
reading a first data bit stored by a first of said volatile memory cells; and
programming the resistive state of a first of said non-volatile memory cells associated with said first volatile memory cell based on said first data bit.

13. A method of restoring data in the memory array of claim 1 , the method comprising:
reading from a second of said non-volatile memory cells a programmed resistive state representing a second data bit; and
writing said second data bit to a second of said volatile memory cells associated with said second non-volatile memory cell.

Assignees

• Commissariat L Energie Atomique Et Aux Energies Alternatives
• Centre Nat Rech Scient

Inventors

• Javerliac Virgile
• Layer Christophe

Classifications

• G11C11/419

  Read-write [R-W] circuits · CPC title

• G11C11/1675

  Writing or programming circuits or methods · CPC title

• G11C11/1673

  Reading or sensing circuits or methods · CPC title

• G11C14/0081 Primary

  and the nonvolatile element is a magnetic RAM [MRAM] element or ferromagnetic cell · CPC title

• G11C11/005

  comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells · CPC title