Synchronizing refresh control circuit for a plurality of slices and semiconductor apparatus using the same

Patent metadata

Field	Value
Publication number	US-9620192-B2
Application number	US-201414567773-A
Country	US
Kind code	B2
Filing date	Dec 11, 2014
Priority date	Sep 5, 2014
Publication date	Apr 11, 2017
Grant date	Apr 11, 2017

Abstract

A semiconductor apparatus with a plurality of slices electrically coupled through through electrodes. Any one slice of the plurality of slices may be configured to generate a refresh cycle signal in response to a refresh command, and transmit the refresh cycle signal to the other slices through the through electrodes. The other slices may be configured to perform refresh operations in synchronization with the refresh cycle signal.

First claim

What is claimed is:

1. A refresh control circuit comprising:
an oscillator configured to generate oscillation signals in response to slice type distinguishment signals;
a control block coupled to the oscillator, and configured to output a refresh cycle signal in response to a refresh command and the oscillation signals, and generate a refresh start signal in response to a slice matching signal, slice identities (IDs) and the refresh cycle signal; and
a comparison block configured to determine whether slice addresses provided from the exterior of the refresh control circuit and the slice IDs correspond to each other, and generate the slice matching signal.

2. The refresh control circuit according to claim 1 , wherein the control block comprises:
a first signal combination unit configured to combine a refresh pulse and a first oscillation signal;
a second signal combination unit configured to combine a second oscillation signal and an oscillation enable signal;
an oscillation enable signal generation unit configured to generate the oscillation enable signal in response to an output of the first signal combination unit, an output of the second signal combination unit and a refresh mode distinguishment signal;
a refresh cycle signal generation unit configured to generate a first pre-refresh cycle signal generated in response to the output of the first signal combination unit, the output of the second signal combination unit and a stack mode distinguishment signal or a second pre-refresh cycle signal received from an exterior of the refresh control circuit, as the refresh cycle signal; and
a self refresh start signal generation unit configured to compare count signals resulting from counting the refresh cycle signal in response to the refresh mode distinguishment signal, with the slice IDs, and generate a self refresh start signal.

3. The refresh control circuit according to claim 2 , wherein a cycle of the second oscillation signal is shorter than a cycle of the first oscillation signal.

4. The refresh control circuit according to claim 2 , wherein the control block further comprises:
an auto refresh start signal generation unit configured to generate an auto refresh start signal in response to the refresh mode distinguishment signal, the refresh cycle signal, and a slice matching signal.

5. A semiconductor apparatus comprising:
a plurality of slices electrically coupled through through-hole electrodes,
wherein any one slice of the plurality of slices is configured to generate a refresh cycle signal in response to a refresh command, and transmit the refresh cycle signal to the other slices through the through-hole electrodes, and
wherein the other slices are configured to perform refresh operations at different timings according to a different pulse, corresponding to a comparison, among pulses of the refresh cycle signal,
wherein the comparison is operated by comparing slice IDs with count signals resulting from counting the refresh cycle signal.

6. The semiconductor apparatus according to claim 5 , wherein the any one slice is a master slice.

7. The semiconductor apparatus according to claim 5 , wherein each of the plurality of slices comprises a refresh control circuit.

8. The semiconductor apparatus according to claim 7 , wherein the refresh control circuit comprises:
an oscillator configured to generate oscillation signals in response to slice type distinguishment signals;
a multiplexing block configured to generate a refresh mode distinguishment signal in response to a stack mode distinguishment signal; and
a control block coupled to the oscillator and the multiplexing block, and configured to output a refresh cycle signal in response to the refresh command and oscillation signals, and generate a refresh start signal in response to slice identities (IDs) and the refresh cycle signal.

9. The semiconductor apparatus according to claim 8 , wherein the control block comprises:
a first signal combination unit configured to combine a refresh pulse and a first oscillation signal;
a second signal combination unit configured to combine a second oscillation signal and an oscillation enable signal;
an oscillation enable signal generation unit configured to generate the oscillation enable signal in response to an output of the first signal combination unit, an output of the second signal combination unit and the refresh mode distinguishment signal;
a refresh cycle signal generation unit configured to generate a first pre-refresh cycle signal which is generated in response to the output of the first signal combination unit, the output of the second signal combination unit and the stack mode distinguishment signal or a second pre-refresh cycle signal received from an exterior of the semiconductor apparatus, as the refresh cycle signal; and
a self refresh start signal generation unit configured to compare count signals resulting from counting the refresh cycle signal in response to the refresh mode distinguishment signal, with the slice IDs, and generate a self refresh start signal.

10. The semiconductor apparatus according to claim 9 , wherein a cycle of the second oscillation signal is shorter than a cycle of the first oscillation signal.

11. The semiconductor apparatus according to claim 8 , wherein the control block further comprises:
an auto refresh start signal generation unit configured to generate an auto refresh start signal in response to the refresh mode distinguishment signal, the refresh cycle signal and a slice matching signal.

12. The semiconductor apparatus according to claim 8 , wherein the control block is configured to generate the refresh start signal in response to a slice matching signal.

13. The semiconductor apparatus according to claim 12 , further comprising:
a comparison block configured to determine whether slice addresses provided from the exterior and the slice IDs correspond to each other, and generate the slice matching signal.

Assignees

• Sk Hynix Inc

Inventors

• Kim Chang Hyun

Classifications

• G11C11/40611 Primary

  External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh · CPC title

• G11C11/40615

  Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs · CPC title

• G11C11/40618

  Refresh operations over multiple banks or interleaving · CPC title