Magnetic memory

Patent metadata

Field	Value
Publication number	US-9620189-B2
Application number	US-201514947643-A
Country	US
Kind code	B2
Filing date	Nov 20, 2015
Priority date	Mar 14, 2013
Publication date	Apr 11, 2017
Grant date	Apr 11, 2017

Abstract

A magnetic memory according to an embodiment includes at least one MTJ element, the MTJ element including: a magnetic multilayer structure including a first magnetic layer in which a direction of magnetization is fixed, a second magnetic layer in which a direction of magnetization is changeable, and a tunnel barrier layer located between the first and second magnetic layers; a first electrode provided on a first surface of the magnetic multilayer structure; a second electrode provided on a second surface of the magnetic multilayer structure; an insulating film provided on a side surface of the magnetic multilayer structure; and a control electrode provided on the side surface of the magnetic multilayer structure with the insulating film located therebetween, a voltage being applied to the control electrode in a read operation, which increases an energy barrier for changing the magnetization of the second magnetic layer.

First claim

The invention claimed is:

1. A magnetic memory comprising at least one element, the element comprising:
a multilayer structure including a first magnetic layer in which a direction of magnetization is fixed, a second magnetic layer in which a direction of magnetization is changeable, and a nonmagnetic layer between the first magnetic layer and the second magnetic layer, the multilayer structure having a first surface, a second surface opposed to the first surface, and a side surface different from the first surface and the second surface;
a first electrode disposed on the first surface of the multilayer structure and electrically connected to the first magnetic layer;
a second electrode disposed on the second surface of the multilayer structure and electrically connected to the second magnetic layer;
an insulating film disposed on the side surface of the multilayer structure;
a control electrode disposed on the side surface of the multilayer structure with the insulating film located therebetween;
a voltage applying circuit that applies a first voltage to the control electrode in a write operation; and
a write circuit that flows a write current between the first electrode and the second electrode to write information to the element.

2. The memory according to claim 1 , wherein when the write circuit writes the information to the element, the voltage applying circuit applies the first voltage to the control electrode so that a potential of the control electrode is identical with a potential of the second magnetic layer, or an energy barrier for changing the magnetization of the second magnetic layer is reduced.

3. The memory according to claim 1 , wherein the magnetization of the first and the second magnetic layers is perpendicular to a face thereof opposed to the nonmagnetic layer.

4. The memory according to claim 1 , wherein the magnetization of the first and the second magnetic layers is parallel to a face thereof opposed to the nonmagnetic layer.

5. The memory according to claim 1 , wherein the control electrode surrounds the entire side surface of the second magnetic layer.

6. The memory according to claim 1 , wherein the control electrode is divided into a plurality of portions each disposed on a part of the side surface of the second magnetic layer with the insulating layer located therebetween.

7. The memory according to claim 1 , wherein the control electrode faces side surfaces of the first and second magnetic layers.

8. The memory according to claim 1 , wherein the at least one element includes two or more elements arranged in a matrix form, in which the control electrodes of the elements on a common row are connected to each other.

9. The memory according to claim 1 , further comprising:
a readout circuit that flows a read current between the first electrode and the second electrode to read information from the element, wherein the voltage applying circuit applies a second voltage to the control electrode in a read operation, and a polarity of the second voltage is opposite to a polarity of the first voltage.

10. A magnetic memory comprising:
at least one element, the element including:
a multilayer structure including a first magnetic layer in which a direction of magnetization is fixed, a second magnetic layer in which a direction of magnetization is changeable, and a nonmagnetic layer between the first magnetic layer and the second magnetic layer, and the multilayer structure having a first surface, a second surface opposed to the first surface, and a side surface different from the first surface and the second surface;

a first electrode disposed on the first surface of the multilayer structure and electrically connected to the first magnetic layer;
a second electrode disposed on the second surface of the multilayer structure and electrically connected to the second magnetic layer;
an insulating layer disposed on the side surface of the multilayer structure;
a control electrode disposed on the side surface of the multilayer structure with the insulating layer located therebetween;
a selection transistor including a source and a drain, one of which is electrically connected to one of the first and the second electrodes;
a first wiring line electrically connected to a gate of the selection transistor;
a second wiring line electrically connected to the other of the first and the second electrodes;
a third wiring line electrically connected to the other of the source and the drain of the selection transistor;
a fourth wiring line electrically connected to the control electrode;
a voltage applying circuit that is electrically connected to the fourth wiring line and applies a first voltage to the control electrode; and
a write circuit that is connected to the first, second, and third wiring lines and flows a write current between the first electrode and the second electrode to write information to the element.

11. The memory according to claim 10 , wherein when the write circuit writes the information to the element, the voltage applying circuit applies the first voltage to the control electrode so that a potential of the control electrode is identical to a potential of the second magnetic layer, or an energy barrier for changing magnetization of the second magnetic layer is reduced.

12. The memory according to claim 10 , wherein the magnetization of the first and the second magnetic layers is perpendicular to a face thereof opposed to the nonmagnetic layer.

13. The memory according to claim 10 , wherein the magnetization of the first and the second magnetic layers is parallel to a face thereof opposed to the nonmagnetic layer.

14. The memory according to claim 10 , wherein the control electrode is disposed to surround the entire side surface of the second magnetic layer.

15. The memory according to claim 10 , wherein the control electrode is divided into a plurality of portions each located on a part of the side surface of the second magnetic layer with the insulating layer located therebetween.

16. The memory according to claim 10 , wherein the control electrode faces side surfaces of the first and second magnetic layers.

17. The memory according to claim 10 , wherein the at least one element includes two or more elements arranged in a matrix form, in which the control electrodes of the elements on a common row are connected with each other.

18. The memory according to claim 10 , further comprising:
a readout circuit that flows a read current between the first electrode and the second electrode to read information from the element, wherein the voltage applying circuit applies a second voltage to the control electrode in a read operation, a polarity of the second voltage is opposite to a polarity of the first voltage.

19. The memory according to claim 10 , wherein the voltage applying circuit applies the first voltage to the control electrode in a write operation.

Assignees

• Toshiba Kk

Inventors

• Shimomura Naoharu
• Kitagawa Eiji
• Amano Minoru
• Saida Daisuke
• Yakushiji Kay
• Nozaki Takayuki
• Yuasa Shinji
• Fukushima Akio
• Imamura Hiroshi
• Kubota Hitoshi

Classifications

• G11C11/1673

  Reading or sensing circuits or methods · CPC title

• G11C11/165

  Auxiliary circuits · CPC title

• H01L29/82

  Electricity · mapped topic

• H01F10/3254

  the spacer being semiconducting or insulating, e.g. for spin tunnel junction [STJ] · CPC title

• H01F10/3286

  Spin-exchange coupled multilayers having at least one layer with perpendicular magnetic anisotropy · CPC title