Method for driving electro-optic displays

Patent metadata

Field	Value
Publication number	US-9620066-B2
Application number	US-201113018829-A
Country	US
Kind code	B2
Filing date	Feb 1, 2011
Priority date	Feb 2, 2010
Publication date	Apr 11, 2017
Grant date	Apr 11, 2017

Abstract

A large area display comprises multiple sub-units arranged in rows and columns. Each sub-unit has associated row and column drivers, with the column driver driving the column electrodes of all the sub-units a column. A chip select means provides a separate chip select signal to each row of sub-units, so that only one row of sub-units are scanned at a time, and all the sub-units in the selected row are scanned simultaneously. Column data are supplied to the column drivers as a linear series of column data values; and delayed Gate Start Pulse signals are fed to the column drivers in each column of sub-units after the first so that these column drivers receive the delayed Gate Start Pulse signals and apply the appropriate column data values to their associated column electrodes.

First claim

The invention claimed is:

1. A method of driving a large area display comprising a plurality of sub-units arranged in a plurality of rows and columns, each sub-unit having an associated row driver and an associated column driver, the sub-units within each column being interconnected such that the associated column driver drives the column electrodes of all the sub-units within the column such that the plurality of sub-units of the large area display are scanned as a single display, the method comprising:
sequentially providing a separate chip select signal to each row driver associated with a row of sub-units,
sequentially scanning each row of pixels in the row of sub-units for which the associated row driver has received the chip select signal so that only the rows of pixels within a single row of sub-units is scanned at any one time,
supplying column data to a first shift register of a first column drivers as a linear series of column data values under the control of a Gate Start Pulse signal and a Gate Clock signal, the Gate Start Pulse signal indicating the start of a new row of data to the first shift register and the Gate Clock signal indicating that a new column data value is to be supplied to the first shift register, and
supplying the column data to a second shift register of a second column driver as a linear series of column data values under the control of a delayed Gate Start Pulse signal and the Gate Clock signal, the delayed Gate Start Pulse signal indicating the start of a new row of data to the second shift register and the Gate Clock signal indicating that a new column data value is to be supplied to the second shift register.

2. A method according to claim 1 wherein the Gate Start Pulse and Gate Clock signals are provided to a programmable logic device which generates the delayed Gate Start Pulse signal at a time appropriate for the second column driver to begin receiving data.

3. A method according to claim 2 wherein the column data are supplied to the first and second column drivers as a linear series of column data extending across all the columns in all the sub-units of a row of sub-units, and the delayed Gate Start Pulse signal causes bytes 1 to N of the linear series of data (where N is an integer equal to the number of columns in the sub-units of the first column) to be placed in the first shift registers of the first column driver, and bytes (N+1) to 2N to be placed in the second shift register of the second column driver.

4. A large area display comprising:
a plurality of sub-units arranged in a plurality of rows and columns, each sub-unit having an associated row driver and an associated column driver, the sub-units within each column being interconnected such that the associated column driver drives the column electrodes of all the sub-units within the column;
chip select means for providing a separate chip select signal to each row of sub-units, so that in the row of sub-units for which the associated row driver has received the chip select signal, only the rows of pixels within a single row of sub-units is scanned at any one time;
column data supply means for supplying column data to the column drivers as a linear series of column data values;
means for feeding, for each row scanned, delayed Gate Start Pulse signals to the column drivers in each column of sub-units after the first so that the column drivers in each column of sub-units after the first receive the delayed Gate Start Pulse signals and apply the appropriate column data values to their associated column electrodes; and
wherein the plurality of sub-units of the large area display are scanned as a single display.

5. A large area display according to claim 4 wherein the means for feeding delayed Gate Start Pulse signals comprises means for generating Gate Start Pulse and Gate Clock signals, the Gate Start Pulse signal indicating the start of a new row of data and the Gate Clock signal indicating that a new column data value is to be supplied, and a programmable logic device which receives the Gate Start Pulse and Gate Clock signals and generates the delayed Gate Start Pulse signals.

6. A large area display according to claim 5 wherein the column data supply means is arranged to supply the column data to the column drivers as a linear series of column data extending across all the columns in all the sub-units of a row of sub-units, and the means for feeding delayed Gate Start Pulse signals are arranged to cause bytes I to N of the linear series of data (where N is a integer equal to the number of columns in the sub-units of the first column) to be placed in shift registers of the column drivers in the first column of sub-units, and bytes (N+1) to 2N to be placed in shift registers of the column drivers in the second column of sub-units.

7. A large area display according to claim 4 wherein at least one of the sub-units is provided, along an edge where it abuts another sub-unit, with optical means arranged to reduce the apparent width of a gap between the sub-units.

8. A large area display according to claim 7 wherein the optical means comprises a lens molded into the viewing surface of the sub-unit.

9. A large area display according to claim 4 wherein at least one of the sub-units is provided with an electro-optic medium which continues over an edge of the sub-unit where it abuts another sub-unit.

10. A large area display according to claim 4 comprising a rotating bichromal member or electrochromic electro-optic medium.

11. A large area display according to claim 4 comprising an electrophoretic medium which itself comprises a plurality of electrically charged particles disposed in a fluid and capable of moving through the fluid under the influence of an electric field.

12. A large area display according to claim 11 wherein the electrically charged particles and the fluid are confined within a plurality of capsules or microcells.

13. A large area display according to claim 11 wherein the electrically charged particles and the fluid are present as a plurality of discrete droplets surrounded by a continuous phase comprising a polymeric material.

14. An electro-optic display according to claim 11 wherein the fluid is gaseous.

Assignees

• Bishop Seth J
• E Ink Corp

Inventors

• Bishop Seth J

Classifications

• G09G3/38

  using electrochromic devices · CPC title

• G09G3/3453

  based on rotating particles or microelements · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G3/2092

  Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto (suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165) · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title