Two level memory full line writes

Patent metadata

Field	Value
Publication number	US-9619396-B2
Application number	US-201514670857-A
Country	US
Kind code	B2
Filing date	Mar 27, 2015
Priority date	Mar 27, 2015
Publication date	Apr 11, 2017
Grant date	Apr 11, 2017

Abstract

A memory controller receives a memory invalidation request that references a line of far memory in a two level system memory topology with far memory and near memory, identifies an address of the near memory corresponding to the line, and reads data at the address to determine whether a copy of the line is in the near memory. Data of the address is to be flushed to the far memory if the data includes a copy of another line of the far memory and the copy of the other line is dirty. A completion is sent for the memory invalidation request to indicate that a coherence agent is granted exclusive access to the line. With exclusive access, the line is to be modified to generate a modified version of the line and the address of the near memory is to be overwritten with the modified version of the line.

First claim

What is claimed is:

1. An apparatus comprising:
a memory controller to access a two level memory, wherein the two level memory comprises a near memory and a far memory, the near memory is to serve as a cache for the far memory, and the memory controller is to:
receive a particular memory invalidation request, wherein the particular memory invalidation request is to reference a particular line of far memory;
identify a particular address of near memory associated with the particular line;
read the particular address of near memory to determine whether a copy of the line is in the near memory, wherein the memory controller is to flush data of the particular address to the far memory if the data identified in the read comprises a copy of another line of far memory and the copy of the other line comprises modified data; and
send a completion for the particular memory invalidation request to indicate that a coherence agent is granted an exclusive copy of the particular line, wherein the exclusive copy of the particular line is to be modified to generate a modified version of the particular line and the particular address of near memory is to be overwritten with the modified version of the particular line.

2. The apparatus of claim 1 , wherein the completion is to be sent prior to completion of any reads and writes to far memory responsive to the particular memory invalidation requests.

3. The apparatus of claim 1 , wherein the memory controller is further to:
identify from the read that a copy of a line in far memory other than the particular line is stored in the particular address of the near memory;
identify that the copy of the line other than the particular line comprises modified data; and
overwrite the line in far memory to include the modified data.

4. The apparatus of claim 3 , wherein a copy of the particular line is not to be written to the particular address prior to the particular address of near memory being overwritten with the modified version of the particular line.

5. The apparatus of claim 1 , wherein the memory controller is further to:
receive a write request to write the modified version of the particular line to the particular address of the near memory; and
cause the particular address of the near memory to be overwritten with the modified version of the particular line.

6. The apparatus of claim 5 , wherein the write request is received from a coherence agent.

7. The apparatus of claim 5 , wherein the write request is to cause directory state of the particular line to transition from modified to invalid.

8. The apparatus of claim 1 , wherein directory state of the copy of the line in the particular address is to be identified in the read.

9. The apparatus of claim 8 , wherein if another line of far memory is identified in the read, directory state of the particular line is to be assumed to be an any (A) state.

10. The apparatus of claim 1 , wherein the memory controller is included in a buffered memory chip.

11. The apparatus of claim 10 , wherein the particular memory invalidation request is to be received over a buffered memory interface.

12. The apparatus of claim 11 , wherein the buffered memory interface is separate from a general purpose input/output (GPIO) interface and the buffered memory interface comprises a physical layer based on a physical layer of the general purpose input/output (GPIO) interface.

13. The apparatus of claim 1 , wherein the particular memory invalidation request is one of a plurality of memory invalidation requests.

14. The apparatus of claim 13 , wherein the particular memory invalidation request corresponds to a request indicating an upcoming full line write of the particular line.

15. The apparatus of claim 1 , wherein no writes or reads of far memory are to be performed in response to the particular memory invalidation request when the read reveals a clean copy of a line other than the particular line in the particular address of near memory.

16. The apparatus of claim 1 , wherein directory state of the particular line is not changed directly in response to the particular memory invalidation request.

17. A method comprising:
receiving a particular memory invalidation request, wherein the particular memory invalidation request references a particular line of far memory in a two level system memory topology, and the two level system memory topology comprises the far memory and near memory;
identifying a particular address of the near memory corresponding to the particular line;
reading the particular address of the near memory to determine whether a copy of the line is in the near memory, wherein data of the particular address is to be flushed to the far memory if the data comprises a copy of another line of the far memory and the copy of the other line comprises modified data; and
sending a completion for the particular memory invalidation request to indicate that a coherence agent is granted an exclusive copy of the particular line, wherein the exclusive copy of the particular line is to be modified to generate a modified version of the particular line and the particular address of the near memory is to be overwritten with the modified version of the particular line.

18. At least one non-transitory machine accessible storage medium having code stored thereon, the code when executed on a machine, causes the machine to:
receive a particular memory invalidation request, wherein the particular memory invalidation request references a particular line of far memory in a two level system memory topology, and the two level system memory topology comprises the farm memory and near memory;
identify a particular address of the near memory corresponding to the particular line;
read the particular address of the near memory to determine whether a copy of the line is in the near memory, wherein the memory controller is to flush data of the particular address to the far memory if the data comprises a copy of another line of the far memory and the copy of the other line comprises modified data; and
send a completion for the particular memory invalidation request to indicate that a coherence agent is granted an exclusive copy of the particular line, wherein the exclusive copy of the particular line is to be modified to generate a modified version of the particular line and the particular address of the near memory is to be overwritten with the modified version of the particular line.

19. A system comprising:
a buffer chip;
two layer memory to be accessed through the buffer chip, wherein the two layer memory comprises near memory and far memory; and
a processor block coupled to the buffer chip by a memory access link;
wherein the buffer chip comprises a memory controller to:
receive a particular memory invalidation request, wherein the particular memory invalidation request references a particular line of far memory;
identify a particular address of near memory corresponding to the particular line;
read the particular address of near memory to determine whether a copy of the line is in the near memory, wherein the memory controller is to flush data of the particular address to the far memory if the data comprises a copy of another line of far memory and the copy of the other line comprises modified data; and
send a completion for the particular memory invalidation request to indicate that a coherence agent is granted an exclusive copy of the particular line, wherein the exclusive copy of the particular line is to be modified to generate a modified version of the particular lin

Assignees

• Intel Corp

Inventors

• Blankenship Robert G
• Chamberlain Jeffrey D
• Liu Yen-Cheng
• Geetha Vedaraman

Classifications

• G06F2212/1016

  Performance improvement · CPC title

• G06F12/0891 Primary

  using clearing, invalidating or resetting means · CPC title

• G06F13/16

  for access to memory bus (G06F13/28 takes precedence) · CPC title

• G06F12/126

  with special data handling, e.g. priority of data or instructions, handling errors or pinning · CPC title

• G06F12/0893

  Caches characterised by their organisation or structure · CPC title