Detection of hardware errors using periodically synchronized redundant transactions and comparing results from cores of a multi-core processor

Patent metadata

Field	Value
Publication number	US-9619356-B2
Application number	US-201514963296-A
Country	US
Kind code	B2
Filing date	Dec 9, 2015
Priority date	Aug 8, 2013
Publication date	Apr 11, 2017
Grant date	Apr 11, 2017

Abstract

A method for detecting errors in hardware including running a transaction on a plurality of cores, wherein each of the cores runs a respective copy of the transaction, periodically synchronizing the transaction on the cores throughout execution of the transaction, comparing results of the transaction on the cores, and determining an error in one or more of the cores.

First claim

What is claimed is:

1. A method for detecting errors in hardware, the method comprising:
running a transaction on a plurality of cores, wherein each of the cores runs a respective copy of the transaction;
periodically synchronizing the transaction on the cores throughout execution of the transaction;
comparing results of the transaction on the cores;
determining an error in one or more of the cores; and
copying a thread of the transaction from a first core of the plurality of cores to one or more second cores of the plurality of cores before running the transaction on the plurality of cores, wherein the first core and the one or more second cores are components of a multi-core processor.

2. The method of claim 1 , wherein comparing results of the transaction on the cores further comprises recording data about the thread upon determining a difference between the results of the transaction on the cores.

3. The method of claim 2 , wherein the data includes at least one of a start and end program counter (PC) of the transaction, a timestamp of when the transaction ran, and which cores the transaction was run on.

4. A computer program product for detecting errors in hardware, the computer program product comprising:
a non-transitory computer readable storage medium having computer readable program code embodied therewith, the non-transitory computer readable program code comprising:
computer readable program code configured to run a transaction on a plurality of cores, wherein each of the cores runs a respective copy of the transaction;
computer readable program code configured to periodically synchronize the transaction on the cores throughout execution of the transaction;
computer readable program code configured to compare results of the transaction on the cores;
computer readable program code configured to determine an error in one or more of the cores; and
computer readable program code configured to copy a thread of the transaction from a first core of the plurality of cores to one or more second cores of the plurality of cores before running the transaction on the plurality of cores, wherein the first core and the one or more second cores are components of a multi-core processor.

5. The computer program product of claim 4 , wherein the computer readable program code configured to compare results of the transaction on the cores further comprises computer readable program code configured to record data about the thread upon determining a difference between the results of the transaction on the cores.

6. The computer program product of claim 5 , wherein the data includes at least one of a start and end program counter (PC) of the transaction, a timestamp of when the transaction ran, and which cores the transaction was run on.

7. A system for testing hardware using multithreaded software, the system comprising:
a redundant transaction hardware configured to run a transaction of the multithreaded software redundantly and to periodically synchronize redundant instances of the transaction executed by the redundant transaction hardware throughout execution of the transaction;
a module configured to detect errors in the redundant transaction hardware based on differences detected between said redundant instances of the transaction executed by the redundant transaction hardware; and
a multi-core processor, wherein the redundant transaction hardware is configured to copy a thread of the transaction from a first core of a plurality of cores to one or more second cores of the plurality of cores before running the transaction on the plurality of cores, wherein the first core and the one or more second cores are components of the multi-core processor.

Assignees

• IBM

Inventors

• Cain Iii Harold W
• Daly David M
• Ekanadham Kattamuri
• Huang Michael C
• Moreira Jose E
• Serrano Mauricio J

Classifications

• G06F11/26

  Functional testing · CPC title

• G06F11/273 Primary

  Tester hardware, i.e. output processing circuits {(G06F11/263 takes precedence)} · CPC title

• G06F11/2242

  in multi-processor systems, e.g. one processor becoming the primary tester (G06F11/2736 takes precedence) · CPC title

• G06F11/263

  Generation of test inputs, e.g. test vectors, patterns or sequences {; with adaptation of the tested hardware for testability with external testers} · CPC title

• G06F11/1608 Primary

  Error detection by comparing the output signals of redundant hardware (G06F11/1629, G06F11/1666 take precedence; error detection or correction in information storage based on relative movement between record carrier and transducer G11B20/18; checking static stores for correct operation G11C29/00; for logic circuits H03K19/003, H03K19/007; for pulse counters or frequency dividers H03K21/40) · CPC title