Write mechanism for storage class memory

Patent metadata

Field	Value
Publication number	US-9619174-B2
Application number	US-201113992809-A
Country	US
Kind code	B2
Filing date	Dec 30, 2011
Priority date	Dec 30, 2011
Publication date	Apr 11, 2017
Grant date	Apr 11, 2017

Abstract

Storage class memory may be used in an architecture to achieve high performance, high reliability, high compatibility. In some embodiments, reads may be handled in a conventional way used in a memory based model. However writes do not use a memory based model but instead correspond to a storage based model. The hybrid nature can be achieved by setting the storage class memory to be write protected so that all writes must go through a software based block device interface. In some embodiments, the software based block device interface prevents erroneous writes to the storage class memory.

First claim

What is claimed is:

1. A method comprising:
setting a page in storage class memory to read only by setting a page table entry bit;
changing the page in the storage class memory to be writable for a batch of memory writes by resetting the page table entry bit;
writing to said storage class memory using a storage based model using an input/output controller to set or reset the bit, said interface to prevent erroneous writes to said storage class memory; and
protecting said memory by writing to a buffer and transferring a batch of data in said buffer to said memory.

2. The method of claim 1 including reorganizing blocks in said buffer to enable said blocks to be written as a group to said memory.

3. The method of claim 2 including reorganizing to identify contiguous blocks.

4. The method of claim 1 including changing said memory to writeable before writing from said buffer.

5. The method of claim 4 including changing said memory to read only after writing to said memory.

6. The method of claim 1 including writing to a storage class memory including phase change memory.

7. The method of claim 1 including detecting an idle period and in response writing to said memory.

8. The method of claim 1 including writing to said memory when said buffer is full.

9. The method of claim 1 wherein transferring includes using a memory copy.

10. A non-transitory computer readable medium storing instructions executed by a controller to:
set a page in storage class memory to read only by setting a page table entry bit;
change the page in the storage class memory to be writable for a batch of memory writes by resetting the page table entry bit;
write to said storage class memory using a storage based model using an input/output controller to set or reset the bit, said interface to prevent erroneous writes to said storage class memory; and
protect said memory by writing to a buffer and transferring a batch of data in said buffer to said memory.

11. The medium of claim 10 further storing instructions to reorganize blocks in said buffer to enable said blocks to be written as a group to said memory.

12. The medium of claim 11 further storing instructions to reorganize to identify contiguous blocks.

13. The medium of claim 10 further storing instructions to change said memory to writeable before writing from said buffer.

14. The medium of claim 13 further storing instructions to change said memory to read only after writing to said memory.

15. The medium of claim 10 further storing instructions to write to a storage class memory including phase change memory.

16. The medium of claim 10 further storing instructions to detect an idle period and in response writing to said memory.

17. The medium of claim 10 further storing instructions to write to said memory when said buffer is full.

18. The medium of claim 10 further storing instructions to transfer using a memory copy.

19. An apparatus comprising:
a storage class memory;
an input/output controller coupled to said memory;
a processor, coupled to said memory controller, to set a page in storage class memory to read only by setting a page table entry bit, change the page in the storage class memory to be writable for a batch of memory writes by resetting the page table entry bit, and write to said storage class memory using a storage based model using the input/output controller to set or reset the bit, said interface to prevent erroneous writes to said storage class memory said processor to protect said memory by writing to a buffer and transferring a batch of data in said buffer to said memory.

20. The apparatus of claim 19 , said processor to reorganize blocks in said buffer to enable said blocks to be written as a group to said memory.

21. The apparatus of claim 20 , said processor to reorganize to identify contiguous blocks.

22. The apparatus of claim 19 , said processor to change said memory to writeable before writing from said buffer.

23. The apparatus of claim 22 , said processor to change said memory to read only after writing to said memory.

24. The apparatus of claim 19 , wherein said memory is a phase change memory.

25. The apparatus of claim 19 , said processor to detect an idle period and in response writing to said memory.

26. The apparatus of claim 19 , said processor to write to said memory when said buffer is full.

27. The apparatus of claim 19 , said processor to transfer using a memory copy.

Assignees

• Chen Feng
• Mesnier Michael P
• Intel Corp

Inventors

• Chen Feng
• Mesnier Michael P

Classifications

• G06F12/1009

  using page tables, e.g. page table structures · CPC title

• G06F12/1433

  for a module or a part of a module · CPC title

• G06F12/0246

  in block erasable memory, e.g. flash memory · CPC title

• G06F3/0611 Primary

  in relation to response time · CPC title

• G06F12/14

  Protection against unauthorised use of memory {or access to memory} · CPC title