Circuit configuration of a touch panel controller IC

US9619058B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9619058-B2
Application numberUS-201414581174-A
CountryUS
Kind codeB2
Filing dateDec 23, 2014
Priority dateDec 31, 2013
Publication dateApr 11, 2017
Grant dateApr 11, 2017

How to read this patent

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A circuit configuration for touch panel controller IC includes a substrate including electrode pins arranged along four border edges thereof for signal transmission, and a controller mounted on the substrate and surrounded by the electrode pins and including processing units arranged in one same direction in a parallel manner, electric contacts arranged in three rows at three sides around the processing units and respectively electrically connected to the electrode pins of the substrate by respective lead wires and steering wires respectively electrically connected between the processing units and the electric contacts. Arranging the processing units in one same direction in a parallel manner minimizes differences in environmental conditions in exposure graphic definition and etch rate, thereby obtaining better circuit component process uniformity, and thus, the variation among the processing units after fabrication can be insignificant and better sensing accuracy can be achieved.

First claim

Opening claim text (preview).

What the invention claimed is: 1. A circuit configuration for touch panel controller integrated circuit (“IC”), comprising: a substrate comprising a plurality of electrode pins arranged along opposing front and rear border edges and opposing left and right border edges thereof for signal transmission, and a plurality of lead wires respectively extended from said electrode pins toward a center part of said substrate; and a controller mounted on said substrate and surrounded by said electrode pins, said controller comprising a plurality of processing units, all of the plurality of processing units being arranged in a single direction in a parallel manner in the form of a rectangular array that defines opposing front and rear sides and opposing left and right sides corresponding to the opposing front and rear border edges and opposing left and right border edges of said substrate, a plurality of electric contacts respectively electrically connected with the respective opposite ends of the lead wires that are respectively connected to the electrode pins at the front, left and right border edges of said substrate, and a plurality of steering lead wires respectively electrically connected between said processing units and said electric contacts, the plurality of electric contacts including first to third parts that are respectively arranged along the front, left and right sides around said processing units, wherein the pitch of the first part of the plurality of electric contacts is larger than pitch of said processing units. 2. The circuit configuration for touch panel controller IC as claimed in claim 1 , wherein said controller further comprises a plurality of first input/output units respectively electrically connected between said processing units and said steering lead wires, said first input/output units being arranged in the same direction in a parallel manner relative to said processing units. 3. The circuit configuration for touch panel controller IC as claimed in claim 2 , wherein the pitch of said first input/output units is approximately equal to the pitch of said processing units. 4. The circuit configuration for touch panel controller IC as claimed in claim 1 , wherein said controller further comprises a plurality of first input/output units respectively electrically connected between said electric contacts and said steering lead wires, said first input/output units being arranged in three rows respectively disposed in parallel to the three rows of said electric contacts. 5. The circuit configuration for touch panel controller IC as claimed in claim 4 , wherein the pitch of said first input/output units is larger than the pitch of said processing units. 6. The circuit configuration for touch panel controller IC as claimed in claim 1 , wherein each said processing unit comprises therein an analog-to-digital converter adapted for converting an external touch panel analog sensing signal into a digital signal. 7. The circuit configuration for touch panel controller IC as claimed in claim 6 , wherein each said processing unit further comprises therein a current-to-voltage converter electrically connected between said analog-to-digital converter and one said electric contact and adapted for converting a current signal into a voltage signal. 8. The circuit configuration for touch panel controller IC as claimed in claim 1 , wherein said controller further comprises a digital processing unit disposed a rear side relative to said processing units and electrically connected with said processing units, a plurality of second electric contacts arranged in a row along a rear side of said digital processing unit opposite to said processing units and respectively connected with the respective opposite ends of the lead wires that are respectively connected to the electrode pins at the rear border edge of said substrate, and a plurality of second input/output units respectively electrically connected between said digital processing unit and said second electric contacts. 9. The circuit configuration for touch panel controller IC as claimed in claim 1 , wherein a first half of the first part of the plurality of electric contacts is arranged adjacent to the second part of the plurality of electric contacts, a second half of the first part of the plurality of electric contacts is arranged adjacent to the third part of the plurality of electric contacts, a number of the electric contacts in the first half of the first part of the plurality of electric contacts and a number of the electric contacts in the second part of the plurality of electric contacts are equal to a half of a number of the processing units, a number of the electric contacts in the second half of the first part of the plurality of electric contacts and a number of the electric contacts in the third part of the plurality of electric contacts are equal to the half of the number of the processing units, and the number of the electric contacts in the second part of the plurality of electric contacts is equal to the number of the electric contacts in the third part of the plurality of electric contacts. 10. The circuit configuration for touch panel controller IC as claimed in claim 1 , wherein numbers of the electric contacts in the first to third parts of the plurality of electric contacts are equal to numbers of electrode pins of the substrate arranged on respective sides of the substrate.

Assignees

Inventors

Classifications

  • between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

  • not being orthogonal to a side surface of the chip, e.g. fan-out arrangements · CPC title

  • Plan-view shape, i.e. in top view · CPC title

  • Manufacturing, i.e. details related to manufacturing processes specially suited for touch sensitive devices · CPC title

  • G06F3/041Primary

    Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means · CPC title

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What does patent US9619058B2 cover?
A circuit configuration for touch panel controller IC includes a substrate including electrode pins arranged along four border edges thereof for signal transmission, and a controller mounted on the substrate and surrounded by the electrode pins and including processing units arranged in one same direction in a parallel manner, electric contacts arranged in three rows at three sides around the p…
Who is the assignee on this patent?
Egalax_Empia Tech Inc
What technology area does this patent fall under?
Primary CPC classification G06F3/041. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Apr 11 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).