Array substrate and liquid crystal display panel

Patent metadata

Field	Value
Publication number	US-9618810-B2
Application number	US-201514766757-A
Country	US
Kind code	B2
Filing date	Mar 10, 2015
Priority date	Feb 11, 2015
Publication date	Apr 11, 2017
Grant date	Apr 11, 2017

Abstract

An array substrate is disclosed, and has a substrate. A first metal layer, a first insulation layer, a second metal layer, a second insulation layer, and a pixel electrode layer are disposed on the substrate successively. A plurality of first through holes and a plurality of second through holes are disposed on the position of a link line, so as to expose the first metal line and the second metal line. The first metal line is electrically connected to the second metal line through a conductive line of the pixel electrode layer. Thus, the problem of vertical and parallel light lines of a drain discharge module can be efficiently improved.

First claim

What is claimed is:

1. An array substrate, comprising:
a substrate;
a first metal layer disposed on the substrate, wherein the first metal layer is formed with a gate of a thin film transistor and a scan line within a display area, and a first metal line within a non-display area;
a first insulation layer disposed on the first metal layer, wherein the first insulation layer isolates the first metal layer from a second metal layer;
the second metal layer disposed on the first insulation layer; wherein the second metal layer is formed with a source of the thin film transistor, a drain of the thin film transistor and a data line within the display area, and a second metal line within the non-display area;
a second insulation layer disposed on the second metal layer, wherein the second insulation layer isolates the second metal layer from a pixel electrode layer;
the pixel electrode layer disposed on the second insulation layer; wherein the pixel electrode layer comprises pixel electrodes within the display area and a conductive line within the non-display area;
wherein the first metal line, the second metal line and the conductive line are overlapped with each other to be a link line, a plurality of first through holes and a plurality of corresponding second through holes are disposed on the link line; the first through holes expose the first metal line; the second through holes expose the second metal line; the first metal line in the first through hole is connected to the second metal line in the corresponding second through hole through the conductive line; the first through hole penetrates the second insulation layer, the second metal layer and the first insulation layer within the non-display area; the second through hole penetrates the second insulation layer within the non-display area; each of the first through holes is corresponding to two of the second through holes, wherein the second through holes are disposed at two sides of the first through hole.

2. The array substrate according to claim 1 , wherein the array substrate further comprises a scan driving chip and a data driving chip, the scan driving chip is electrically connected to the scan line through the link line, and the data driving chip is electrically connected to the data line through the link line.

3. The array substrate according to claim 1 , wherein a plurality of the first through holes and a plurality of the corresponding second through holes are uniformly disposed on the link line.

4. An array substrate, comprising:
a substrate;
a first metal layer disposed on the substrate, wherein the first metal layer is formed with a gate of a thin film transistor and a scan line within a display area, and a first metal line within a non-display area;
a first insulation layer disposed on the first metal layer, wherein the first insulation layer isolates the first metal layer from a second metal layer;
the second metal layer disposed on the first insulation layer; wherein the second metal layer is formed with a source of the thin film transistor, a drain of the thin film transistor and a data line within the display area, and a second metal line within the non-display area;
a second insulation layer disposed on the second metal layer, wherein the second insulation layer isolates the second metal layer from a pixel electrode layer;
the pixel electrode layer disposed on the second insulation layer; wherein the pixel electrode layer comprises pixel electrodes within the display area and a conductive line within the non-display area;
wherein the first metal line, the second metal line, and the conductive line are overlapped with each other to be a link line, a plurality of first through holes and a plurality of corresponding second through holes are disposed on the link line; the first through holes expose the first metal line; the second through holes expose the second metal line; the first metal line in the first through hole is connected to the second metal line in the corresponding second through hole through the conductive line.

5. The array substrate according to claim 4 , wherein the first through hole penetrates the second insulation layer, the second metal layer, and the first insulation layer within the non-display area; and the second through hole penetrates the second insulation layer within the non-display area.

6. The array substrate according to claim 4 , wherein each of the first through holes is corresponding to two of the second through holes, wherein the second through holes are disposed at two sides of the first through hole.

7. The array substrate according to claim 4 , wherein the array substrate further comprises a scan driving chip and a data driving chip, the scan driving chip is electrically connected to the scan line through the link line, and the data driving chip is electrically connected to the data line through the link line.

8. The array substrate according to claim 4 , wherein a plurality of the first through holes and a plurality of the corresponding second through holes are uniformly disposed on the link line.

9. An liquid crystal display panel, comprising an array substrate, a color filter substrate, and a liquid crystal cell disposed between the array substrate and the color filter substrate, wherein the array substrate comprises:
a substrate;
a first metal layer disposed on the substrate, wherein the first metal layer is formed with a gate of a thin film transistor and a scan line within a display area, and a first metal line within a non-display area;
a first insulation layer disposed on the first metal layer, wherein the first insulation layer isolates the first metal layer from a second metal layer;
the second metal layer disposed on the first insulation layer; wherein the second metal layer is formed with a source of the thin film transistor, a drain of the thin film transistor and a data line within the display area, and a second metal line within the non-display area;
a second insulation layer disposed on the second metal layer, wherein the second insulation layer isolates the second metal layer from a pixel electrode layer;
the pixel electrode layer disposed on the second insulation layer; wherein the pixel electrode layer comprises pixel electrodes within the display area and a conductive line within the non-display area;
wherein the first metal line, the second metal line, and the conductive line are overlapped with each other to be a link line, a plurality of first through holes and a plurality of corresponding second through holes are disposed on the link line; the first through holes expose the first metal line; the second through holes expose the second metal line; the first metal line in the first through hole is connected to the second metal line in the corresponding second through hole through the conductive line.

10. The liquid crystal display panel according to claim 9 , wherein the first through hole penetrates the second insulation layer, the second metal layer and the first insulation layer within the non-display area; and the second through hole penetrates the second insulation layer within the non-display area.

11. The liquid crystal display panel according to claim 9 , wherein each of the first through hole is corresponding to two of the second through holes, wherein the second through holes are disposed at two sides of the first through hole.

12. The liquid crystal display panel according to claim 9 , wherein the array substrate further comprises a scan driving chip and a data driving chip, the scan driving chip is electrically connected to the scan line through the link line, and the data driving chip is electrically connected to the data line t

Assignees

• Shenzhen China Star Optoelect

Inventors

• Fu Yanfeng

Classifications

• G02F1/1345 Primary

  Conductors connecting electrodes to cell terminals · CPC title

• G02F1/136227

  Through-hole connection of the pixel electrode to the active element through an insulation layer · CPC title