Semiconductor device

Patent metadata

Field	Value
Publication number	US-9617143-B2
Application number	US-201414585634-A
Country	US
Kind code	B2
Filing date	Dec 30, 2014
Priority date	Dec 13, 2013
Publication date	Apr 11, 2017
Grant date	Apr 11, 2017

Abstract

A method of forming a semiconductor device comprises bonding a capping wafer and a base wafer to form a wafer package. The base wafer comprises a plurality of chip package portions. The capping wafer comprises a plurality of isolation trenches. Each isolation trench of the plurality of isolation trenches is configured to substantially align with a corresponding chip package portion of the plurality of chip package portions. The method also comprises separating the wafer package into a plurality of chip packages. Each chip package of the plurality of chip packages comprises at least one chip package portion of the plurality of chip package portions.

First claim

What is claimed is:

1. A method of forming a semiconductor device comprising: bonding a capping wafer and a base wafer to form a wafer package, the base wafer comprising a plurality of chip package portions, the capping wafer comprising a plurality of isolation trenches, and each isolation trench of the plurality of isolation trenches being configured to substantially align with a corresponding chip package portion of the plurality of chip package portions; separating the wafer package into a plurality of chip packages, each chip package of the plurality of chip packages comprising at least one chip package portion of the plurality of chip package portions; forming a plurality of communication openings in the capping wafer, the plurality of communication openings comprising a first pair of communication openings configured to substantially align a first chip package portion of the plurality of chip package portions, and a second pair of communication openings configured to substantially align with a second chip package portion of the plurality of chip package portions; depositing a dielectric material in the plurality of communication openings; and forming the plurality of isolation trenches between the pairs of communication openings.

2. The method of claim 1 , wherein at least two chip packages of the plurality of chip packages are configured to be handled in different environmental conditions.

3. The method of claim 1 , wherein at least two chip packages of the plurality of chip packages are configured to perform different operations.

4. The method of claim 1 , further comprising:
bonding at least two chip packages of the plurality of chip packages together with a molding compound;
forming a redistribution layer over the at least two chip packages of the plurality of chip packages and at least a portion of the molding compound;
forming an insulation layer over the molding compound and the redistribution layer; and
forming a plurality of openings in the insulation layer thereby exposing at least a portion of the redistribution layer.

5. The method of claim 2 , wherein a first chip package of the at least two chip packages of the plurality of chip packages is formed as a high vacuum pressure device, and a second chip package of the at least two chip packages of the plurality of chip packages is formed as a low vacuum pressure device.

6. The method of claim 4 , wherein a first chip package of the at least two chip packages of the plurality of chip packages is one of an accelerometer or a gyroscope, and a second chip package of the at least two chip packages of the plurality of chip packages is one of an accelerometer, a gyroscope or a pressure sensor, different from the first chip package.

7. The method of claim 4 , further comprising:
forming a plurality of under bump layers in the plurality of openings; and
forming a plurality of solder bumps over the under bump layers.

8. The method of claim 4 , further comprising:
bonding a CMOS chip package together with the at least two chip packages of the plurality of chip packages using the molding compound.

9. The method of claim 7 , wherein the redistribution layer is also formed over the CMOS chip package.

10. A semiconductor device comprising: a plurality of chip packages, each chip package of the plurality of chip packages comprising a base wafer portion of a base wafer bonded to a capping wafer portion of a capping wafer, wherein the chip packages of the plurality of chip packages are separate components derived from the capping wafer and the base wafer, at least two chip packages of the plurality of chip packages are configured to be handled in different environmental conditions; wherein at least two chip packages of the plurality of chip packages are bonded together with a molding compound, and the semiconductor device further comprises: a redistribution layer over the at least two chip packages of the plurality of chip packages and at least a portion of the molding compound; an insulation layer over the molding compound and the redistribution layer; a plurality of openings in the insulation layer exposing a portion of the redistribution layer; and a plurality of conductive elements in the plurality of openings.

11. The semiconductor device of claim 10 , wherein a first chip package of the at least two chip packages of the plurality of chip packages is a high vacuum pressure device, and a second chip package of the at least two chip packages of the plurality of chip packages is a low vacuum pressure device.

12. The semiconductor device of claim 10 , wherein at least two chip packages of the plurality of chip packages are configured to perform different operations.

13. The semiconductor device of claim 10 , wherein the conductive elements comprise an under bump layer and a solder bump.

14. The semiconductor device of claim 10 , wherein the conductive elements comprise a conductive pillar.

15. The semiconductor device of claim 10 , further comprising: a CMOS chip package bonded together with the at least two chip packages of the plurality of chip packages by the molding compound.

16. The semiconductor device of claim 12 , wherein a first chip package of the at least two chip packages of the plurality of chip packages is one of an accelerometer or a gyroscope, and a second chip package of the at least two chip packages of the plurality of chip packages is one of an accelerometer, a gyroscope or a pressure sensor, different from the first chip package.

17. A method of forming a semiconductor device comprising:
forming a base wafer comprising a plurality of chip package portions;
bonding a capping wafer and the base wafer to form a wafer package;
separating the wafer package into a plurality of chip packages, each chip package of the plurality of chip packages comprising at least one chip package portion of the plurality of chip package portions; and
bonding at least two chip packages of the plurality of chip packages together,
wherein the at least two chip packages of the plurality of chip packages are configured to be handled under different pressure conditions.

18. The method of claim 17 , wherein at least two chip package portions of the plurality of chip package portions are formed having different configurations, causing at least two chip package portions of the plurality of chip package portions to perform different operations.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Cheng Chun-Wen
• Peng Jung-Huei
• Tsai Shang-Ying
• Tsai Hung-Chia
• Teng Yi-Chuan

Classifications

• H10W72/012

  of bump connectors, dummy bumps or thermal bumps · CPC title

• B81C1/00333

  Aspects relating to packaging of MEMS devices, not covered by groups B81C1/00269 - B81C1/00325 · CPC title

• B81B7/04

  Networks or arrays of similar microstructural devices · CPC title

• B81C1/0023

  Packaging together an electronic processing unit die and a micromechanical structure die (MEMS packages B81B7/0032; MEMS packaging processes B81C1/00261) · CPC title

• B81B7/02 Primary

  containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems [MEMS] (B81B7/04 takes precedence) · CPC title