Wireless-transmitter circuits including power digital-to-amplitude converters

Patent metadata

Field	Value
Publication number	US-9614541-B2
Application number	US-201514873177-A
Country	US
Kind code	B2
Filing date	Oct 1, 2015
Priority date	Oct 1, 2014
Publication date	Apr 4, 2017
Grant date	Apr 4, 2017

Abstract

Circuits comprising: digital-to-amplitude converter (DAC), comprising: binary weighted switching transistors (BWSTs), each having gate coupled to amplitude control bit ACB, and wherein the drain of each of the BWSTs are connected together and wherein the source of each of the BWSTs are connected together; transistor M 1 having gate coupled to input signal and first bias voltage BV 1 and source coupled to the drains of the BWSTs; transistor M 2 having gate coupled to BV 2 and source coupled to the drain of M 1 ; transistor M 3 having gate coupled to BV 3 and source coupled to the drain of M 2 ; transistor having gate coupled to BV 4 , source coupled to the drain of M 3 ; and inverter having input coupled to another ACB and having output coupled to the output of the DAC and the drain of M 4.

First claim

What is claimed is:

1. A circuit for a transmitter, comprising:
at least one digital-to-amplitude converter (DAC) each having an input and an output, each comprising:
a plurality of binary weighted switching transistors, each having a gate coupled to one of a plurality of control bits, a drain, and a source, wherein the drains of the plurality of binary weighted switching transistors are connected together and wherein the sources of the plurality of binary weighted switching transistors are connected to ground;
a first transistor having a gate coupled to an input signal from the input and a first bias voltage, a source coupled to the drains of the plurality of binary weighted switching transistors, and a drain;
a second transistor having a gate coupled to a second bias voltage, a source coupled to the drain of the first transistor, and a drain;
a third transistor having a gate coupled to a third bias voltage, a source coupled to the drain of the second transistor, and a drain;
a fourth transistor having a gate coupled to a fourth bias voltage, a source coupled to the drain of the third transistor, and a drain coupled to the output of the DAC;
an inductor having a first side coupled to the drain of the fourth transistor and having a second side; and
a capacitor having a first side connected to ground and having a second side coupled to the second side of the inductor and to a voltage that is controlled by another control bit;
and for each of the at least one DAC, an antenna coupled to the output of the DAC.

2. The circuit of claim 1 , further comprising:
a first variable gain amplifier (VGA) that receives a first digital input and that provides a first VGA output;
a first continuous time linear equalizer (CTLE) that receives the first VGA output and that produces a first CTLE output; and
a demultiplexer that receives the first CTLE output and a clock signal and that produces the plurality of control bits and the another control bit.

3. The circuit of claim 2 , further comprising:
a second VGA that receives a second digital input and that provides a second VGA output; and
a second CTLE that receives the second VGA output and that produces the clock signal.

4. The circuit of claim 1 , further comprising a bias voltage generator comprising:
a voltage divider formed from four equally sized, serial resistors that produces a first voltage, a second voltage, a third voltage, and a fourth voltage;
a first transistor having a gate and a drain connected to ground and having a source;
a second transistor having a gate connected to the first voltage, a drain coupled to a first bias voltage output and the source of the first transistor, and a source;
a third transistor having a gate connected to the second voltage, a drain coupled to a second bias voltage output and the source of the second transistor, and a source; and
a fourth transistor having a gate connected to the third voltage, a drain coupled to a third bias voltage output and the source of the third transistor, and a source coupled to a fourth bias voltage output and a current source.

5. The circuit of claim 4 , wherein the current source is variable.

6. The circuit of claim 4 , wherein the first bias voltage output, the second bias voltage output, the third bias voltage output, and the fourth bias voltage output provide the first bias voltage, the second bias voltage, the third bias voltage, and the fourth bias voltage, respectively.

7. The circuit of claim 1 , wherein the at least one DAC includes a plurality of DACs and each of the plurality of DACs is part of a digital polar transmitter element that also comprises a quadrature hybrid, a phase shifter, and a limiting amplifier, wherein a drive signal drives the quadrature hybrid, the quadrature hybrid outputs an in-phase signal and a quadrature signal, the phase shifter receives the in-phase signal and the quadrature signal and provides an output signal that is shifted according to one of a plurality of phase signals, and the limiting amplifier receives the output signal from the phase shifter and outputs the input signal to the DAC, and wherein a scan chain provides the plurality of phase signals.

8. A circuit for a transmitter, comprising:
at least one digital-to-amplitude converter (DAC) each having an input and an output, each comprising:
a plurality of binary weighted switching transistors, each having a gate coupled to one of a plurality of control bits, a drain, and a source, wherein the drains of the plurality of binary weighted switching transistors are connected together and wherein the sources of the plurality of binary weighted switching transistors are connected to ground;
a first transistor having a gate coupled to an input signal from the input and a first bias voltage, a source coupled to the drains of the plurality of binary weighted switching transistors, and a drain;
a second transistor having a gate coupled to a second bias voltage, a source coupled to the drain of the first transistor, and a drain;
a third transistor having a gate coupled to a third bias voltage, a source coupled to the drain of the second transistor, and a drain;
a fourth transistor having a gate coupled to a fourth bias voltage, a source coupled to the drain of the third transistor, and a drain coupled to the output of the DAC;
a transmission line having a first side coupled to the drain of the fourth transistor and having a second side; and
a capacitor having a first side connected to ground and having a second side coupled to the second side of the transmission line and to a voltage that is controlled by another control bit; and

for each of the at least one DAC, an antenna coupled to the output of the DAC.

9. The circuit of claim 8 , further comprising:
a first variable gain amplifier (VGA) that receives an a first digital input and that provides a first VGA output;
a first continuous time linear equalizer (CTLE) that receives the first VGA output and that produces a first CTLE output; and
a demultiplexer that receives the first CTLE output and a clock signal and that produces the plurality of control bits and the another control bit.

10. The circuit of claim 9 , further comprising:
a second VGA that receives a second digital input and that provides a second VGA output; and
a second CTLE that receives the second VGA output and that produces the clock signal.

11. The circuit of claim 8 , further comprising a bias voltage generator comprising:
a voltage divider formed from four equally sized, serial resistors that produces a first voltage, a second voltage, a third voltage, and a fourth voltage;
a first transistor having a gate and a drain connected to ground and having a source;
a second transistor having a gate connected to the first voltage, a drain coupled to a first bias voltage output and the source of the first transistor, and a source;
a third transistor having a gate connected to the second voltage, a drain coupled to a second bias voltage output and the source of the second transistor, and a source; and
a fourth transistor having a gate connected to the third voltage, a drain coupled to a third bias voltage output and the source of the third transistor, and a source coupled to a fourth bias voltage output and a current source.

12. The circuit of claim 11 , wherein the current source is variable.

13. The circuit of claim 11 , wherein the first bias voltage output, the second bias voltage output, the third bias voltage output, and the fourth bias voltage output provide the first bias voltage, the second bias voltage, the third bias voltage, and the fourth bias voltage, respectively.

14. Th

Assignees

• Chakrabarti Anandaroop
• Krishnaswamy Harish
• Univ Columbia

Inventors

• Chakrabarti Anandaroop
• Krishnaswamy Harish

Classifications

• H03M1/745

  with weighted currents · CPC title

• H04L25/03878

  Line equalisers; line build-out devices · CPC title

• H03G3/001

  Digital control of analog signals · CPC title

• H03M1/78

  using ladder network · CPC title

• H03G3/3036 Primary

  in high-frequency amplifiers or in frequency-changers (H03G3/3052, H03G3/32, H03G3/34 take precedence) · CPC title