Input/output (I/O) driver implementing dynamic gate biasing of buffer transistors

Patent metadata

Field	Value
Publication number	US-9614529-B1
Application number	US-201615012696-A
Country	US
Kind code	B1
Filing date	Feb 1, 2016
Priority date	Feb 1, 2016
Publication date	Apr 4, 2017
Grant date	Apr 4, 2017

Abstract

An input/output (I/O) driver that includes circuitry for over-voltage protection of first and second FETs coupled in series between a first rail and an output, and third and fourth FETs coupled between the output and a second rail. The circuitry is configured to generate a gate bias voltage for the second FET that transitions from high to low bias voltages state when the output voltage (V PAD ) begins transitioning from low to high logic voltages, and transitions back to the high bias voltage while V PAD continues to transition towards the high logic voltage. Further, the circuitry is configured to generate a gate bias voltage for the third FET that transitions from low to high bias voltages when V PAD begins transitioning from high to low logic voltages, and transitions back to the low bias voltage while V PAD continues to transition towards the low logic voltage.

First claim

What is claimed is:

1. An apparatus, comprising:
a pull-up circuit including a first transistor and a second transistor coupled in series between a first voltage rail and an output;
a pull-down circuit including a third transistor and a fourth transistor coupled in series between the output and a second voltage rail;
a first voltage generator configured to generate a first bias voltage responsive to a voltage at the output, wherein a control input of the second transistor is configured to receive the first bias voltage, the first bias voltage configured to transition from a first relatively high voltage to a first relatively low voltage approximately when the voltage at the output begins transitioning from a first low logic voltage towards a first high logic voltage due to the pull-up circuit coupling the first voltage rail to the output and the pull-down circuit decoupling the output from the second voltage rail, and the first bias voltage also configured to transition from the first relatively low voltage to the first relatively high voltage while the output voltage continues to transition from the first low logic voltage towards the first high logic voltage; and
a second voltage generator configured to generate a second bias voltage responsive to the voltage at the output, wherein a control input of the third transistor is configured to receive the second bias voltage, the second bias voltage configured to transition from a second relatively low voltage to a second relatively high voltage approximately when the output voltage begins transitioning from the first high logic voltage towards the first low logic voltage due to the pull-down circuit coupling the output to the second voltage rail and the pull-up circuit decoupling the first voltage rail from the output, and the second bias voltage also configured to transition from the second relatively high voltage to the second relatively low voltage while the output voltage continues to transition from the first high logic voltage towards the first low logic voltage.

2. The apparatus of claim 1 , wherein a time interval beginning with the first bias voltage transitioning from the first relatively high voltage to the first relatively low voltage and ending with the first bias voltage transitioning from the first relatively low voltage to the first relatively high voltage is a function of a rate at which the output voltage transitions from the first low logic voltage towards the first high logic voltage.

3. The apparatus of claim 1 , wherein a time interval beginning with the second bias voltage transitioning from the second relatively low voltage to the second relatively high voltage and ending with the second bias voltage transitioning from the second relatively high voltage to the second relatively low voltage is a function of a rate at which the output voltage transitions from the first high logic voltage towards the first low logic voltage.

4. The apparatus of claim 1 , wherein the first bias voltage is configured to transition from the first relatively low voltage to the first relatively high voltage in response to the output voltage increasing to a defined voltage level.

5. The apparatus of claim 1 , wherein the second bias voltage is configured to transition from the second relatively high voltage to the second relatively low voltage in response to the output voltage decreasing to a defined voltage level.

6. The apparatus of claim 1 , further comprising a predriver configured to generate a third voltage, the third voltage configured to transition from a second high logic voltage to a second low logic voltage in response to an input voltage transitioning from a third low logic voltage to a third high logic voltage, wherein the first bias voltage is configured to transition from the first relatively high voltage to the first relatively low voltage in response to the third voltage transitioning from the second high logic voltage to the second low logic voltage.

7. The apparatus of claim 1 , further comprising a predriver configured to generate a third voltage, the third voltage configured to transition from a second low logic voltage to a second high logic voltage in response to an input voltage transitioning from a third high logic voltage to a third low logic voltage, wherein the second bias voltage is configured to transition from the second relatively low voltage to the second relatively high voltage in response to the third voltage transitioning from the second low logic voltage to the second low logic voltage.

8. The apparatus of claim 1 , wherein the first relatively high voltage is different than the second relatively high voltage, and wherein the first relatively low voltage is different than the second relatively low voltage.

9. The apparatus of claim 1 , further comprising a third voltage generator configured to generate a third voltage applied to a node between the first transistor and the second transistor in response to the output voltage transitioning to or being at the first low logic voltage, wherein the third voltage is substantially halfway between the first high logic voltage and the first low logic voltage.

10. The apparatus of claim 1 , further comprising a third voltage generator configured to generate a third voltage applied to a node between the third transistor and the fourth transistor in response to the output voltage transitioning to or being at the first high logic voltage, wherein the third voltage is substantially halfway between the first high logic voltage and the first low logic voltage.

11. A method, comprising:
coupling a first voltage rail to an output by turning on a first transistor and a second transistor coupled in series between the first voltage rail and the output in response to an input voltage transitioning from a first low logic voltage to a first high logic voltage;
decoupling a second voltage rail from the output by turning off a third transistor and a fourth transistor coupled in series between the output and the second voltage rail in response to the input voltage transitioning from the first low logic voltage to the first high logic voltage, wherein a voltage at the output transitions from a second low logic voltage towards a second high logic voltage in response to the coupling of the first voltage rail to the output and the decoupling of the second voltage rail from the output;
coupling the second voltage rail to the output by turning on the third transistor and the fourth transistor in response to the input signal transitioning from the first high logic voltage to the first low logic voltage;
decoupling the first voltage rail from the output by turning off the first transistor and the second transistor in response to the input signal transitioning from the first high logic voltage to the low logic voltage, wherein the output voltage transitions from the second high logic voltage towards the second low logic voltage in response to the coupling of the second voltage rail to the output and the decoupling of the first voltage rail from the output;
transitioning a first bias voltage applied to a control input of the second transistor from a first relatively high voltage to a first relatively low voltage approximately when the output voltage begins transitioning from the second low logic voltage towards the second high logic voltage;
transitioning the first bias voltage, responsive to the voltage at the output, from the first relatively low voltage to the first relatively high voltage while the output voltage continues to transition from the second low logic voltage towards the second high logic voltage;
transitioning a second bias voltage applied to a control input of the third transistor from a second rel

Assignees

• Qualcomm Inc

Inventors

• Chen Wilson
• Tan Chiew-Guan
• Jalilizeinali Reza

Classifications

• H03K19/018507 Primary

  Interface arrangements · CPC title

• H03K19/0016

  by using a control or a clock signal, e.g. in order to apply power supply · CPC title

• H03K19/018514

  with at least one differential stage (H03K19/018528 and H03K19/018542 take precedence) · CPC title