Signal referencing for memory

US9614331B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9614331-B2
Application numberUS-201313925400-A
CountryUS
Kind codeB2
Filing dateJun 24, 2013
Priority dateJun 24, 2013
Publication dateApr 4, 2017
Grant dateApr 4, 2017

How to read this patent

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  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Apparatus, systems, and methods for signal referencing for memory are described. In one embodiment, connector for a memory device comprises a housing having a first panel and a second panel opposite the first panel to be positioned adjacent a circuit board, the first panel and second panel defining a slot to receive a portion of the memory device, a first plurality of electrically conductive pins disposed in the slot and proximate the first panel to establish electrical connections with a plurality of electrical connectors on the memory device, wherein at least one of the first plurality of pins is a ground pin and a layer of conductive material disposed proximate the second surface. The ground pin is electrically coupled to the layer of conductive material. Other embodiments are also disclosed and claimed.

First claim

Opening claim text (preview).

The invention claimed is: 1. A connector for a memory device, comprising: a housing having a first panel and a second panel opposite the first panel to be positioned adjacent a circuit board, the first panel and second panel defining a slot to receive a portion of the memory device; a first plurality of electrically conductive pins disposed in the slot along the first panel to establish electrical connections with conductive pins on a first side of the memory device, wherein at least one of the first plurality of pins is a ground pin; at least one aperture formed in the first panel and positioned at a location corresponding to a location of the ground pin; a layer of conductive material formed on the first panel such that the conductive material fills the at least one aperture to define a tab to provide an electrical connection with the ground pin, wherein the layer of conductive material forms a first ground plane to which the first plurality of pins is referenced; and a second plurality of electrically conductive pins disposed in the slot along the second panel to establish electrical connections with conductive pins on a second side of the memory device, where the second plurality of pins is referenced to a second ground plane at the circuit board. 2. The connector of claim 1 , wherein the housing is formed from a material that is not electrically conductive. 3. The connector of claim 1 , wherein the tab extends through a portion of the first panel. 4. A circuit board for an electronic device, comprising: a dielectric substrate comprising a plurality of circuit traces; and a connector for a memory device coupled to the circuit board, the connector comprising: a housing positioned adjacent the circuit board, the housing comprising a first panel and a second panel opposite the first panel, the first panel and the second panel defining a slot to receive a portion of the memory device; a first plurality of electrically conductive pins disposed in the slot along the first panel to establish electrical connections with conductive pins on a first side of the memory device, wherein at least one of the first plurality of pins is a ground pin; at least one aperture formed in the first panel and positioned at a location corresponding to a location of the ground pin; a layer of conductive material formed on the first panel such that the conductive material fills the at least one aperture to define a tab to provide an electrical connection with the ground pin, wherein the layer of conductive material forms a first ground plane to which the first plurality of pins is referenced; and a second plurality of electrically conductive pins disposed in the slot along the second panel to establish electrical connections with conductive pins on a second side of the memory device, wherein the second plurality of pins is referenced to a second ground plane at the circuit board. 5. The circuit board of claim 4 , wherein the housing is formed from a material that is not electrically conductive. 6. The circuit board of claim 4 , wherein the tab extends through a portion of the first panel. 7. An electronic device, comprising: at least one electronic component; and a circuit board for the electronic device, comprising: a dielectric substrate comprising a plurality of circuit traces; and a connector for a memory device coupled to the circuit board, the connector comprising: a housing positioned adjacent the circuit board, the housing comprising a first panel and a second panel opposite the first panel and, the first panel and second panel defining a slot to receive a portion of the memory device; a first plurality of electrically conductive pins disposed in the slot along the first panel to establish electrical connections with conductive pins on a first side of the memory device, wherein at least one of the first plurality of pins is a ground pin; at least one aperture formed in the first panel and positioned at a location corresponding to a location of the ground pin; a layer of conductive material formed on the first panel such that the conductive material fills the at least one aperture to define a tab to provide an electrical connection with the ground pin, wherein the layer of conductive material forms a first ground plane to which the first plurality of pins is reference; and a second plurality of electrically conductive pins disposed in the slot along the second panel to establish electrical connections with conductive pins on a second side of the memory device, wherein the second plurality of pins is referenced to a second ground plane at the circuit board. 8. The electronic device of claim 7 , wherein the housing is formed from a material that is not electrically conductive. 9. The electronic device of claim 7 , wherein the tab extends through a portion of the first panel. 10. A method to couple a memory device to a circuit board, comprising: positioning the memory device in a housing adjacent a circuit board, the housing comprising: a first panel and a second panel opposite the first panel and positioned adjacent the circuit board, the first panel and the second panel defining a slot to receive a portion of the memory device; a first plurality of electrically conductive pins disposed in the slot along the first panel to establish electrical connections with a plurality of conductive pins on a first side of the memory device, wherein at least one of the first plurality of pins is a ground pin; at least one aperture formed in the first panel and positioned at a location corresponding to a location of the ground pin; a layer of conductive material formed on the first panel such that the conductive material fills the at least one aperture to define a tab to provide an electrical connection with the ground pin, wherein the layer of conductive material forms a first ground plane to which the first plurality of pins is referenced; and a second plurality of electrically conductive pins disposed in the slot along the second panel to establish electrical connections with conductive pins on a second side of the memory device, wherein the second plurality of pins is referenced to a second ground plane at the circuit board. 11. The method of claim 10 , further comprising: securing the memory device in the slot.

Assignees

Inventors

Classifications

  • Coupling device provided on the PCB · CPC title

  • Dielectric material made conductive, e.g. plastic material coated with metal · CPC title

  • with component orienting · CPC title

  • High frequency shielding arrangements, e.g. against EMI [Electro-Magnetic Interference] or EMP [Electro-Magnetic Pulse] {(coaxial coupling devices specially adapted for high frequency H01R24/40; for flat or ribbon cable connectors H01R12/774; for coaxial cable H01R9/05)} · CPC title

  • Structural associations of a plurality of mutually-insulated electrical connecting elements, specially adapted for printed circuits, e.g. printed circuit boards [PCB], flat or ribbon cables, or like generally planar structures, e.g. terminal strips, terminal blocks; Coupling devices specially adapted for printed circuits, flat or ribbon cables, or like generally planar structures; Terminals specially adapted for contact with, or insertion into, printed circuits, flat or ribbon cables, or like generally planar structures (printed connections to, or between, printed circuits H05K1/11) · CPC title

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What does patent US9614331B2 cover?
Apparatus, systems, and methods for signal referencing for memory are described. In one embodiment, connector for a memory device comprises a housing having a first panel and a second panel opposite the first panel to be positioned adjacent a circuit board, the first panel and second panel defining a slot to receive a portion of the memory device, a first plurality of electrically conductive pi…
Who is the assignee on this patent?
Intel Corp
What technology area does this patent fall under?
Primary CPC classification H01R13/6599. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Apr 04 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).