Forming conductive STI liners for FinFETs

Patent metadata

Field	Value
Publication number	US-9614059-B2
Application number	US-201514977329-A
Country	US
Kind code	B2
Filing date	Dec 21, 2015
Priority date	Oct 11, 2013
Publication date	Apr 4, 2017
Grant date	Apr 4, 2017

Abstract

An integrated circuit device, and a method of forming, including a semiconductor substrate, isolation regions extending into the semiconductor substrate, a semiconductor strip, and a semiconductor fin overlapping and joined to the semiconductor strip is provided. A first dielectric layer and a second dielectric layer are disposed on opposite sidewalls of the semiconductor strip. The integrated circuit device further includes a first conductive liner and a second conductive liner, wherein the semiconductor strip, the first dielectric layer, and the second dielectric layer are between the first conductive liner and the second conductive line. The first conductive liner and the second conductive liner are between, and in contact with, sidewalls of a first portion and a second portion of the isolation regions.

First claim

What is claimed is:

1. A method of forming a semiconductor device, the method comprising:
forming a first dielectric layer along sidewalls of a fin extending from a substrate;
forming a conductive layer over the first dielectric layer;
forming a second dielectric layer over the conductive layer;
recessing the first dielectric layer, the conductive layer, and the second dielectric layer, thereby exposing an upper portion of the fin;
forming a gate dielectric over the upper portion of the fin; and
forming a gate electrode over the gate dielectric.

2. The method of claim 1 , further comprising, prior to forming the conductive layer, forming a third dielectric layer over the substrate adjacent to the fin, wherein the conductive layer is formed over the third dielectric layer.

3. The method of claim 2 , further comprising, prior to forming the gate dielectric, forming a fourth dielectric layer over the conductive layer, the fourth dielectric layer separating the gate dielectric from the conductive layer.

4. The method of claim 3 , further comprising electrically coupling a voltage source to the conductive layer.

5. The method of claim 4 , wherein the conductive layer comprises a “L” shaped layer extending over an upper surface of the third dielectric layer.

6. The method of claim 1 , wherein the conductive layer comprises a “L” shaped layer extending over an upper surface of the substrate.

7. The method of claim 6 , further comprising, prior to forming the conductive layer, implanting dopants into the substrate using the first dielectric layer as a mask.

8. The method of claim 7 , further comprising, prior to implanting dopants into the substrate, forming a spacer along a sidewall of the first dielectric layer.

9. The method of claim 7 , prior to forming the gate dielectric, forming a third dielectric layer over the conductive layer, the third dielectric layer separating the gate dielectric and the conductive layer.

10. A method of forming a semiconductor device, the method comprising:
etching a semiconductor substrate to form a recess in the semiconductor substrate, wherein an un-recessed portion of the semiconductor substrate between opposite portions of the recess forms a semiconductor strip;
forming a first dielectric layer on sidewalls of the semiconductor strip;
forming a conductive liner on sidewalls of the first dielectric layer;
filling the recess to form an isolation region;
recessing the conductive liner and the isolation region, wherein a portion of the semiconductor strip forms a semiconductor fin over a remaining portion of the isolation region;
forming a gate dielectric on sidewalls and a top surface of the semiconductor fin; and
forming a gate electrode overlying the gate dielectric, wherein the gate electrode and the gate dielectric overlap the conductive liner, and wherein the gate dielectric and the gate electrode form parts of a Fin Field-Effect Transistor (FinFET).

11. The method of claim 10 , further comprising, before forming the conductive liner, implanting a portion of the semiconductor substrate underlying the recess to form a doped region, wherein the conductive liner comprises a horizontal portion overlying and contacting the doped region.

12. The method of claim 10 , further comprising:
before forming the conductive liner, forming a second dielectric layer to cover a bottom of the recess; and
coupling a voltage source to the conductive liner, wherein the voltage source is configured to provide a positive bias voltage or a negative bias voltage to the conductive liner.

13. The method of claim 10 , further comprising:
after recessing the conductive liner and the isolation region and before the forming the gate dielectric, forming a second dielectric layer overlapping the isolation region and the conductive liner.

14. The method of claim 10 , wherein the forming the conductive liner comprises:
forming a doped polysilicon region on the sidewalls of the first dielectric layer, wherein the doped polysilicon region has a conductivity type opposite to a conductivity type of source and drain regions of the FinFET.

15. The method of claim 10 , wherein the forming the conductive liner comprises forming a mid-gap metal layer on the sidewalls of the first dielectric layer.

16. A method of forming a semiconductor device, the method comprising:
forming a fin extending from a substrate;
forming an “L” shaped conductive liner on opposing sidewalls of the fin;
forming a first dielectric layer over the “L” shaped conductive liner, an upper portion of the fin extending above an uppermost surface of the “L” shaped conductive liner and the first dielectric layer;
forming a gate dielectric over the upper portion of the fin; and
forming a gate electrode over the gate dielectric.

17. The method of claim 16 , further comprising, prior to forming the “L” shaped conductive liner, forming a second dielectric layer, the second dielectric layer separating the “L” shaped conductive liner from the fin.

18. The method of claim 17 , further comprising, prior to forming the “L” shaped conductive liner, implanting dopants into the substrate along opposing sides of the fin.

19. The method of claim 18 , further comprising, prior to forming the gate dielectric, forming a third dielectric layer over the “L” shaped conductive liner.

20. The method of claim 16 , further comprising, prior to forming the “L” shaped conductive liner, forming a second dielectric layer over the substrate on opposing sides of the fin, wherein the “L” shaped conductive liner extends over an upper surface of the second dielectric layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Colinge Jean-Pierre

Classifications

• H10P14/416

  of highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers · CPC title

• H10D64/01302

  the insulator being formed after the semiconductor body, the semiconductor being silicon · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10D30/62 Primary

  Fin field-effect transistors [FinFET] · CPC title