AMOLED backplane structure and manufacturing method thereof

US9614017B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9614017-B2
Application numberUS-201514761310-A
CountryUS
Kind codeB2
Filing dateJun 18, 2015
Priority dateMay 13, 2015
Publication dateApr 4, 2017
Grant dateApr 4, 2017

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  1. Title

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  2. Abstract

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  5. First independent claim

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Abstract

Official abstract text for this publication.

The present invention provides an AMOLED backplane structure and a manufacturing method thereof. In each sub-pixel, a TFT substrate (TS) includes a corrugation structure ( 4 ) formed in an area corresponding to an opening ( 71 ) of a pixel definition layer ( 7 ). The corrugation structure ( 4 ) includes a plurality of raised sections ( 41 ) and a recessed section ( 42 ) formed between every two adjacent ones of the raised sections ( 41 ). An upper surface of a portion of the planarization layer ( 5 ) and a portion of a pixel electrode ( 6 ) that correspond to and are located above the corrugation structure ( 4 ) include curved surfaces corresponding to the corrugation structure ( 4 ). The AMOLED backplane structure helps ensure the planarization layer ( 5 ) is smooth and free of abrupt change sites and also makes the pixel electrode ( 6 ) in a form of a curved surface to increase an effective displaying surface, extend the lifespan of the OLED, reduce difficulty of manufacturing, and improve resolution.

First claim

Opening claim text (preview).

What is claimed is: 1. An active matrix organic light emitting display (AMOLED) backplane structure, comprising multiple sub-pixels arranged in an array, wherein in each of the sub-pixels, the AMOLED backplane comprises: a thin-film transistor (TFT) substrate, a planarization layer formed on the TFT substrate, a pixel electrode formed on the planarization layer, a pixel definition layer formed on the pixel electrode, and a photo spacer formed on the pixel definition layer; the TFT substrate comprises therein a switch TFT, a drive TFT, and a capacitor; the pixel definition layer comprises an opening to expose a portion of the pixel electrode the TFT substrate comprises a corrugation structure arranged in an area corresponding to the opening of the pixel definition layer, the corrugation structure comprising a plurality of raised sections and a recessed section formed between every two adjacent ones of the raised sections, the raised sections and the recessed sections having vertical dimensions identical to each other; and an upper surface of a portion of the planarization layer and a portion of the pixel electrode that correspond to and are located above the corrugation structure have curved configurations corresponding to the corrugation structure. 2. The AMOLED backplane structure as claimed in claim 1 , wherein in each of the sub-pixels, the TFT substrate comprises a base plate, first and second gate terminals formed on the base plate and spaced from each other, a gate insulation layer formed on the first and second gate terminals and the base plate, first and second semiconductor layers formed on the gate insulation layer and respectively located on the first and second gate terminals, an etch stop layer formed on the first and second semiconductor layers and the gate insulation layer, a first source terminal formed on the etch stop layer and in contact engagement with the first semiconductor layer, a first drain terminal formed on the etch stop layer and in contact engagement with the first semiconductor layer and the second gate terminal, a second source terminal formed on the etch stop layer and in contact engagement with the second semiconductor layer, a second drain terminal formed on the etch stop layer and in contact engagement with the second semiconductor layer, and a protective layer formed on the etch stop layer, the first source and drain terminals, and the second source and drain terminals; the first gate terminal, the first semiconductor layer, the first source terminal, and the first drain terminal constituting the switch TFT, the second gate terminal, the second semiconductor layer, the second source terminal, and the second drain terminal constituting the drive TFT, the second gate terminal and the second source terminal also constituting the capacitor, the pixel electrode being in contact engagement with the second drain terminal. 3. The AMOLED backplane structure as claimed in claim 2 , wherein the corrugation structure is formed in the protective layer of the TFT substrate. 4. The AMOLED backplane structure as claimed in claim 2 , wherein the corrugation structure is formed in the protective layer and the etch stop layer of the TFT substrate. 5. The AMOLED backplane structure as claimed in claim 2 , wherein in each of the sub-pixels, the TFT substrate further comprises a metal layer formed between the protective layer and the etch stop layer in the area corresponding to the opening of the pixel definition layer and the metal layer is formed simultaneously with the first source and drain terminals and the second source and drain terminals; the corrugation structure being formed on the metal layer. 6. The AMOLED backplane structure as claimed in claim 2 , wherein the protective layer and the etch stop layer comprise a material of silicon nitride, silicon oxide, or a combination thereof; and the first and second gate terminals, the first source and drain terminals and the second source and drain terminals comprise a material of one of molybdenum, titanium, aluminum, and copper, or a combination thereof. 7. The AMOLED backplane structure as claimed in claim 2 , wherein the pixel electrode comprises a material of indium tin oxide (ITO). 8. The AMOLED backplane structure as claimed in claim 1 , wherein the corrugation structure is formed in a portion of or all the sub-pixels. 9. An active matrix organic light emitting display (AMOLED) backplane structure, comprising multiple sub-pixels arranged in an array, wherein in each of the sub-pixels, the AMOLED backplane comprises: a thin-film transistor (TFT) substrate, a planarization layer formed on the TFT substrate, a pixel electrode formed on the planarization layer, a pixel definition layer formed on the pixel electrode, and a photo spacer formed on the pixel definition layer; the TFT substrate comprises therein a switch TFT, a drive TFT, and a capacitor; the pixel definition layer comprises an opening to expose a portion of the pixel electrode; the TFT substrate comprises a corrugation structure arranged in an area corresponding to the opening of the pixel definition layer, the corrugation structure comprising a plurality of raised sections and a recessed section formed between every two adjacent ones of the raised sections, the raised sections and the recessed sections having vertical dimensions identical to each other; and an upper surface of a portion of the planarization layer and a portion of the pixel electrode that correspond to and are located above the corrugation structure have curved configurations corresponding to the corrugation structure; wherein in each of the sub-pixels, the TFT substrate comprises a base plate, first and second gate terminals formed on the base plate and spaced from each other, a gate insulation layer formed on the first and second gate terminals and the base plate, first and second semiconductor layers formed on the gate insulation layer and respectively located on the first and second gate terminals, an etch stop layer formed on the first and second semiconductor layers and the gate insulation layer, a first source terminal formed on the etch stop layer and in contact engagement with the first semiconductor layer, a first drain terminal formed on the etch stop layer and in contact engagement with the first semiconductor layer and the second gate terminal, a second source terminal formed on the etch stop layer and in contact engagement with the second semiconductor layer, a second drain terminal formed on the etch stop layer and in contact engagement with the second semiconductor layer, and a protective layer formed on the etch stop layer, the first source and drain terminals, and the second source and drain terminals; the first gate terminal, the first semiconductor layer, the first source terminal, and the first drain terminal constituting the switch TFT, the second gate terminal, the second semiconductor layer, the second source terminal, and the second drain terminal constituting the drive TFT, the second gate terminal and the second source terminal also constituting the capacitor, the pixel electrode being in contact engagement with the second drain terminal; wherein the corrugation structure is formed in a portion of or all the sub-pixels; and wherein the pixel electrode comprises a material of indium tin oxide (ITO). 10. The AMOLED backplane structure as claimed in claim 9 , wherein the corrugation structure is formed in the protective layer of the TFT substrate. 11. The AMOLED backplane structure as claimed in claim 9 , wherein the corrugation structure is formed in the protective layer and the etch stop layer of the TFT substrate. 12. The AMOLED backplane structure as c

Assignees

Inventors

Classifications

  • characterised by their shape · CPC title

  • Insulating layers formed between TFT elements and OLED elements · CPC title

  • H10D86/451Primary

    characterised by the compositions or shapes of the interlayer dielectrics · CPC title

  • Electricity · mapped topic

  • Electricity · mapped topic

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What does patent US9614017B2 cover?
The present invention provides an AMOLED backplane structure and a manufacturing method thereof. In each sub-pixel, a TFT substrate (TS) includes a corrugation structure ( 4 ) formed in an area corresponding to an opening ( 71 ) of a pixel definition layer ( 7 ). The corrugation structure ( 4 ) includes a plurality of raised sections ( 41 ) and a recessed section ( 42 ) formed between every two…
Who is the assignee on this patent?
Shenzhen China Star Optoelect, Shenzhen China Star Optoelectronics Technolody Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10D86/451. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Apr 04 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).