Exposed die power semiconductor device

Patent metadata

Field	Value
Publication number	US-9613941-B2
Application number	US-201414552442-A
Country	US
Kind code	B2
Filing date	Nov 24, 2014
Priority date	Mar 6, 2014
Publication date	Apr 4, 2017
Grant date	Apr 4, 2017

Abstract

A semiconductor package has a lead frame and a power die. The lead frame has a first die paddle with a cavity formed entirely therethrough. The power die, which has a lower surface, is mounted on the first die paddle such that a first portion of the lower surface is attached to the first die paddle using a solderless die-attach adhesive, and a second portion of the lower surface, is not attached to the first die paddle and abuts the cavity formed in the first die paddle such that the second portion is exposed.

First claim

The invention claimed is:

1. A semiconductor package, comprising:
a lead frame comprising a first die paddle having at least one cavity formed entirely therethrough, and a ledge formed at at least two opposite sides of the at least one cavity, wherein a thickness of the ledge is less than a thickness of the first die paddle;
a first die comprising a lower surface, wherein:
a first portion of the lower surface is attached to the ledge using a die-attach material; and
a second portion of the lower surface that is not attached to the ledge, is exposed to an ambient environment through the at least one cavity, wherein the first die is at least partially embedded in the at least one cavity;

a plurality of bond wires electrically connecting the first die to the lead frame; and
a molding compound encapsulating an upper surface of the lead frame, the bond wires, and an upper portion of the first die,
wherein the semiconductor package is mounted on a printed circuit board after application of the molding compound using solder paste, wherein the solder paste fills at least a portion of the at least one cavity and contacts the second portion of the lower surface of the first die.

2. The semiconductor package of claim 1 , wherein:
the die-attach material is a solderless die-attach adhesive.

3. The semiconductor package of claim 2 , wherein the solderless die-attach adhesive is an epoxy or die-attach tape.

4. The semiconductor package of claim 1 , wherein:
the lead frame further comprises a second die paddle; and
the semiconductor package further comprises a second die mounted on the second die paddle using the die-attach material, wherein the die-attach material of the first die and the second die is cured concurrently.

5. The semiconductor package of claim 1 , wherein the first die has a driving current greater than about 1 ampere.

6. The semiconductor package of claim 1 , further comprising a heat sink attached to the second portion of the lower surface of the first die, wherein an outer surface of the heat sink is exposed.

Assignees

• Xu Yanbo
• Wang Zhijie
• Zong Fei
• Freescale Semiconductor Inc

Inventors

• Xu Yanbo
• Wang Zhijie
• Zong Fei

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W70/681

  comprising holes not having chips therein, e.g. for outgassing, underfilling or bond wire passage · CPC title

• H10W70/682

  comprising holes having chips therein · CPC title

• H10W72/0198

  batch processes · CPC title