Semiconductor device and method for manufacturing a semiconductor device

Patent metadata

Field	Value
Publication number	US-9613930-B2
Application number	US-201314064093-A
Country	US
Kind code	B2
Filing date	Oct 25, 2013
Priority date	Oct 25, 2013
Publication date	Apr 4, 2017
Grant date	Apr 4, 2017

Abstract

A device includes a first semiconductor chip including a first face, wherein a first contact pad is arranged over the first face. The device further includes a second semiconductor chip including a first face, wherein a first contact pad is arranged over the first face, wherein the first semiconductor chip and the second semiconductor chip are arranged such that the first face of the first semiconductor chip faces in a first direction and the first face of the second semiconductor chip faces in a second direction opposite to the first direction. The first semiconductor chip is located laterally outside of an outline of the second semiconductor chip.

First claim

What is claimed is:

1. A method, comprising:
providing an electrically conductive foil attached on a carrier;
exposing at least one portion of the carrier by removing at least one portion of the electrically conductive foil to form at least one cavity in the electrically conductive foil;
attaching a first semiconductor chip to a non-removed portion of the electrically conductive foil, wherein the first semiconductor chip comprises a first contact pad arranged over a first face of the first semiconductor chip and a second contact pad arranged over a second face of the first semiconductor chip, wherein the second face is opposite the first face, wherein the second contact pad is at least one of electrically or thermally coupled to the electrically conductive foil and wherein the first contact pad is electrically coupled to the electrically conductive foil;
attaching a second semiconductor chip to an exposed portion of the carrier inside the at least one cavity;
embedding the first semiconductor chip and the second semiconductor chip at least partially in a non-conductive layer arranged over the carrier; and
after embedding the first semiconductor chip and the second semiconductor chip, forming a first electrically conductive layer over the first semiconductor chip and over the non-conductive layer.

2. The method of claim 1 , comprising: embedding the first semiconductor chip at least partly in the non-conductive layer between the carrier and the first electrically conductive layer.

3. The method of claim 1 , wherein the attaching the first semiconductor chip to the electrically conductive foil comprises one of the following connection techniques: soldering, diffusion soldering, diffusion bonding, conductive adhesive bonding, ultrasonic bonding, and thermal compression.

4. The method of claim 1 , wherein removing the at least one portion of the electrically conductive foil comprises using a first selective etchant configured to etch the electrically conductive foil.

5. The method of claim 2 , comprising: removing the carrier after embedding the first semiconductor chip in the non-conductive layer.

6. The method of claim 4 , wherein removing the carrier comprises using a second selective etchant configured to etch the carrier.

7. The method of claim 1 , wherein the electrically conductive foil contacts the carrier and an etch rate of the electrically conductive foil differs from an etch rate of the carrier.

8. The method of claim 1 , wherein an etch stop layer is arranged between the electrically conductive foil and the carrier.

9. The method of claim 1 , wherein the second semiconductor chip comprises a first contact pad arranged over a first face of the second semiconductor chip and a second contact pad arranged over a second face of the second semiconductor chip, and wherein the second contact pad of the second semiconductor chip is temporarily fixed to the carrier.

10. A method, comprising:
providing an electrically conductive foil attached on a carrier;
exposing at least one portion of the carrier by removing at least one portion of the electrically conductive foil to form at least one cavity in the electrically conductive foil;
attaching a first semiconductor chip to a non-removed portion of the electrically conductive foil, the first semiconductor chip including a first contact pad arranged over a first face of the first semiconductor chip and a second contact pad arranged over a second face of the first semiconductor chip, wherein the second face is opposite the first face, and attaching a second semiconductor chip to an exposed portion of the carrier inside the at least one cavity;
wherein the first face of the first semiconductor chip facing in a first direction opposite to the carrier and a first face of the second semiconductor chip facing in the first direction are approximately located at a same height from the carrier; and
removing the carrier from the conductive foil.

11. The method of claim 10 , wherein a height difference between the first face of the first semiconductor chip and the first face of the second semiconductor chip is smaller than 40 micrometers, or smaller than 10 micrometers.

12. The method of claim 10 , wherein a thickness of the first semiconductor chip lies in a range between 30 micrometers and 150 micrometers; and wherein a thickness of the second semiconductor chip lies in a range between 150 micrometers and 550 micrometers.

13. The method of claim 10 , comprising:
embedding the first semiconductor chip and the second semiconductor chip in at least one first material layer comprising cavities corresponding to positions of the first semiconductor chip and the second semiconductor chip; and
covering the first and second semiconductor chips by at least one second material layer.

14. The method of claim 13 , wherein at least one of the at least one first material layer and the at least one second material layer comprises a glass fiber reinforcement.

15. The method of claim 13 , wherein the at least one first material layer comprises one of a molding resin and a filled polymer film.

Assignees

• Infineon Technologies Ag

Inventors

• Palm Petteri

Classifications

• H10W90/792

  between multiple chips · CPC title

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W90/10

  Configurations of laterally-adjacent chips · CPC title

• H10W80/743

  having disposition changed during the connecting · CPC title