Package-on-package (PoP) device with integrated passive device in a via

Patent metadata

Field	Value
Publication number	US-9613917-B2
Application number	US-201213435809-A
Country	US
Kind code	B2
Filing date	Mar 30, 2012
Priority date	Mar 30, 2012
Publication date	Apr 4, 2017
Grant date	Apr 4, 2017

Abstract

A package for a use in a package-on-package (PoP) device. The package includes a substrate, a polymer layer formed on the substrate, a first via formed in the polymer layer, and a material disposed in the first via to form a first passive device. The material may be a high dielectric constant dielectric material in order to form a capacitor or a resistive material to form a resistor.

First claim

What is claimed is:

1. A package for a use in a package-on-package (PoP) device, comprising:
a substrate;
a polymer layer formed on the substrate;
a first via formed in the polymer layer, the first via having a first sidewall in the polymer layer and a second sidewall in the polymer layer, the first sidewall facing the second sidewall;
a non-conductive material disposed in the first via to form a first passive device, an uppermost surface of the non-conductive material engaging a passivation layer, the passivation layer extending over from the first sidewall to the second sidewall of the polymer layer; and
a first contact and a second contact, the passivation layer and the first passive device being interposed between the first contact and the second contact.

2. The PoP device of claim 1 , wherein the first passive device is at least partially disposed within the first via.

3. The PoP device of claim 1 , wherein the first passive device comprises first and second contacts on opposing sides of the non-conductive material disposed in the first via.

4. The PoP device of claim 1 , wherein the non-conductive material is a dielectric material forming at least one of a capacitor and a resistor.

5. A package for a use in a package-on-package (PoP) device, comprising:
a substrate;
a polymer layer formed on the substrate;
a first via formed in extending from a first side of the polymer layer to a second side of the polymer layer;
a first contact on the first side of the polymer layer;
a second contact on the second side of the polymer layer, wherein the polymer layer is interposed between first contact and the second contact; and
a material disposed in the first via to form a first passive device electrically interposed between the first contact and the second contact, a non-conducting layer extending over and contacting an uppermost surface of the polymer layer and an uppermost surface of the material.

6. The package of claim 5 , wherein the material is a dielectric material and the first passive device is a capacitor.

7. The package of claim 6 , wherein the polymer layer includes a plurality of additional vias filled with the dielectric material to form a plurality of additional capacitors, the capacitor and the additional capacitors electrically coupled together.

8. The package of claim 5 , wherein the material is a resistive material and the first passive device is a resistor.

9. The package of claim 5 , wherein the polymer layer comprises an organic polyimide.

10. The package of claim 5 , wherein the polymer layer comprises an epoxy.

11. The package of claim 5 , wherein the polymer layer includes a second via filled with the material to form a second passive device.

12. The package of claim 5 , wherein the polymer layer encapsulates a logic chip mounted on the substrate.

13. A package-on-package (PoP) device, comprising:
a top package; and
a bottom package operably coupled to the top package, the bottom package including a substrate supporting a polymer layer, the polymer layer including a first via filled with a first material to form a first passive device, the first material engaging a non-conducting layer extending over the polymer layer, an upper surface of the first material being coplanar with an upper surface of the polymer layer, wherein the first material is a first dielectric material and the first passive device is a first capacitor, and wherein a top surface of the first dielectric material is electrically coupled to a first contact and a bottom surface of the first dielectric material is electrically coupled to a second contact.

14. The PoP device of claim 13 , wherein the polymer layer includes a second via filled with the first dielectric material to form a second capacitor.

15. The PoP device of claim 13 , wherein the polymer layer includes a plurality of additional vias filled with the first dielectric material to form a plurality of additional capacitors, the additional capacitors are electrically coupled together.

16. The PoP device of claim 13 , wherein the first material is a first dielectric material and the first passive device is a first capacitor, and wherein the polymer layer includes a second via filled with a second dielectric material to form a second capacitor, the first dielectric material different from the second dielectric material such that the first and second capacitors each provide a different capacitance.

17. The PoP device of claim 13 , wherein the top package incorporates a memory chip.

18. The PoP device of claim 13 , wherein the bottom package incorporates a logic chip encapsulated by the polymer layer.

19. The PoP device of claim 13 , wherein the second contact comprises a conductive material extending along sidewalls of the first via, the conductive material being interposed between the first dielectric material and the polymer layer.

20. The PoP device of claim 19 , wherein an upper surface of the conductive material is level with an upper surface of the first dielectric material.

Assignees

• Hsiao Ching-Wen
• Chen Chen-Shien
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Hsiao Ching-Wen
• Chen Chen-Shien

Classifications

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title