Thin film transistor substrate including a channel length measuring pattern and display panel having the same

Patent metadata

Field	Value
Publication number	US-9613876-B2
Application number	US-201514976492-A
Country	US
Kind code	B2
Filing date	Dec 21, 2015
Priority date	Apr 3, 2015
Publication date	Apr 4, 2017
Grant date	Apr 4, 2017

Abstract

A thin film transistor (TFT) substrate includes a base substrate, a TFT disposed on the base substrate. The TFT includes a gate electrode, a semiconductor layer comprising a channel region, and a source electrode and a drain electrode spaced apart from one another by a length of the channel region. The TFT substrate further includes a gate insulating layer disposed between the gate electrode and the semiconductor layer and a measuring pattern configured to measure a length of the channel region.

First claim

What is claimed is:

1. A thin film transistor (TFT) substrate, comprising:
a base substrate;
a TFT disposed on the base substrate, the TFT comprising:
a gate electrode;
a gate insulating layer disposed on the gate electrode;
a semiconductor layer disposed on the gate insulating layer, the semiconductor layer comprising a channel region;
a source electrode disposed on the semiconductor layer, the source electrode comprising a concave edge; and
a drain electrode disposed on the semiconductor layer and spaced apart from the source electrode by a first distance equal to a length of the channel region;

and
a measuring pattern disposed on the gate insulating layer and electrically insulated from the TFT, the measuring pattern comprising:
a first portion disposed on the gate insulating layer; and
two second portions spaced apart from each other by a second distance, extending parallel in a first direction, and disposed on the first portion,
wherein the concave edge of the source electrode faces the drain electrode in plan view.

2. The TFT substrate of claim 1 , wherein the first distance is within 2% of the second distance.

3. The TFT substrate of claim 1 , wherein a difference between the first distance and the second distance is within 0.1 μm.

4. The TFT substrate of claim 1 , wherein at least one second portion of the measuring pattern comprises the same material as the source electrode.

5. The TFT substrate of claim 4 , wherein at least one second portion of the measuring pattern comprises the same material as the drain electrode.

6. The TFT substrate of claim 1 , wherein the first portion of the measuring pattern comprises the same material as the semiconductor layer.

7. The TFT substrate of claim 1 , wherein the measuring pattern overlaps the gate electrode.

8. A display panel, comprising:
a thin film transistor (TFT) substrate;
a counter substrate facing the TFT substrate; and
a display device disposed between the TFT substrate and the counter substrate,
wherein the TFT substrate comprises:
a base substrate;
a TFT disposed on the base substrate, the TFT comprising:
a gate electrode;
a gate insulating layer disposed on the gate electrode;
a semiconductor layer disposed on the gate insulating layer, the semiconductor layer comprising a channel region;
a source electrode disposed on the semiconductor layer, the source electrode comprising a concave edge; and
a drain electrode disposed on the semiconductor layer and spaced apart from the source electrode by a first distance equal to a length of the channel region;

and
a measuring pattern disposed on the gate insulating layer and electrically insulated from the TFT, the measuring pattern comprising:
a first portion disposed on the gate insulating layer; and
two second portions spaced apart from each other by a second distance, extending parallel in a first direction, and disposed on the first portion,
wherein the concave edge of the source electrode faces the drain electrode in plan view.

9. The display panel of claim 8 , wherein the first distance is within 2% of the second distance.

10. The display panel of claim 8 , wherein a difference between the first distance and the second distance is within 0.1 μm.

11. The display panel of claim 8 , wherein at least one second portion of measuring pattern comprises the same material as the source electrode.

12. The display panel of claim 11 , wherein at least one second portion of the measuring pattern comprises the same material as the drain electrode.

13. The display panel of claim 8 , wherein the first portion of the measuring pattern comprises the same material as the semiconductor layer.

14. The display panel of claim 8 , wherein the measuring pattern overlaps the gate electrode.

15. The display panel of claim 8 , wherein at least a part of the measuring pattern overlaps the display device.

16. A thin film transistor (TFT) substrate, comprising:
a base substrate;
a TFT disposed on the base substrate, the TFT comprising:
a gate electrode;
a gate insulating layer disposed on the gate electrode;
a semiconductor layer disposed on the gate insulating layer, the semiconductor layer comprising a channel region;
a source electrode disposed on the semiconductor layer; and
a drain electrode disposed on the semiconductor layer and spaced apart from the source electrode by a first distance equal to a length of the channel region; and

a measuring pattern disposed on gate insulating layer and electrically insulated from the TFT, the measuring pattern comprising:
a first portion disposed on the gate insulating layer; and
two second portions spaced apart from each other by a second distance, extending parallel in a first direction, and disposed on the first portion.

17. The TFT substrate of claim 16 , wherein the first distance is within 2% of the second distance.

18. The TFT substrate of claim 17 , wherein the measuring pattern is spaced apart from the gate electrode in plan view.

Assignees

• Samsung Display Co Ltd

Inventors

• Cho Yong Tae
• Kim Joong Tae
• Kim In Woo
• Park Kwang Su
• Lee Da Young
• Hwang Min Ha
• Hwang Seong Jun

Classifications

• H10P74/27

  Structural arrangements therefor · CPC title

• H10P74/273 Primary

  Interconnections for measuring or testing, e.g. probe pads · CPC title

• H10D30/674

  characterised by the active materials · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H01L27/1222

  Electricity · mapped topic