Semiconductor device and fabricating method thereof

Patent metadata

Field	Value
Publication number	US-9613871-B2
Application number	US-201514801332-A
Country	US
Kind code	B2
Filing date	Jul 16, 2015
Priority date	Jul 16, 2015
Publication date	Apr 4, 2017
Grant date	Apr 4, 2017

Abstract

A semiconductor device is provided. A substrate includes a first region and a second region. A first wire pattern, extending in a first direction, is formed at a first height from the substrate of the first region. A second wire pattern, extending in a second direction, is formed at a second height from the substrate of the second region. The first height is different from the second height. A first gate electrode, surrounding the first wire pattern, extends in a third direction crossing the first direction. A second gate electrode, surrounding the second wire pattern, extends in a fourth direction crossing the second direction. A first gate insulation layer is formed along a circumference of the first wire pattern and a sidewall of the first gate electrode. A second gate insulation layer is formed along a circumference of the second wire pattern and a sidewall of the second gate electrode.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate including a first region and a second region;
a first wire pattern, extending in a first direction, formed at a first height from the substrate of the first region;
a second wire pattern, extending in a second direction, formed at a second height from the substrate of the second region, wherein the first: height is different from the second height;
a first gate electrode extending in a third direction crossing the first direction and surrounding the first wire pattern;
a second gate electrode extending in a fourth direction crossing the second direction and surrounding the second wire pattern;
a first gate insulation layer formed along a circumference of the first wire pattern and a sidewall of the first gate electrode; and
a second gate insulation layer formed along a circumference of the second wire pattern and a sidewall of the second gate electrode.

2. The semiconductor device of claim 1 , further comprising
a first source/drain which is in contact with the first wire pattern and a second source/drain which is in contact with the second wire pattern,
wherein the first source/drain includes a first epitaxial layer and the second source/drain includes a second epitaxial layer.

3. The semiconductor device of claim 2 ,
wherein the first epitaxial layer is in contact with the first wire pattern and the first gate insulation layer, and
wherein the second epitaxial layer is in contact with the second wire pattern and the second gate insulation layer.

4. The semiconductor device of claim 2 ,
wherein each of the first epitaxial layer and the second epitaxial layer is shaped of at least one of a diamond, a circle and a rectangle.

5. The semiconductor device of claim 1 , further comprising
a first gate spacer disposed on the sidewall of the first gate electrode and a second gate spacer disposed on the sidewall of the second gate electrode,
wherein the first gate insulation layer is further formed along the sidewall of the first gate spacer and the second gate insulation layer is further formed along the sidewall of the second gate spacer.

6. The semiconductor device of claim 1 , further comprising:
a first source/drain disposed on the first wire pattern and a second source/drain disposed on the second wire pattern,
wherein the first source/drain includes a first semiconductor pattern and a second semiconductor pattern stacked one on the other, and
wherein the second source/drain includes a third semiconductor pattern and a fourth semiconductor pattern stacked one on the other.

7. The semiconductor device of claim 6 ,
wherein the second semiconductor pattern is in contact with the first wire pattern, and
wherein the third semiconductor pattern is in contact with the second wire pattern.

8. The semiconductor device of claim 1 , further comprising a third wire pattern, extending in the first direction, formed at a third height from the substrate of the first region,
wherein the second height is greater than the first height, and the third height is greater than the second height.

9. The semiconductor device of claim 8 ,
wherein the first height is measured from a top surface of the substrate to a topmost part of the first wire pattern,
wherein the second height is measured from the top surface of the substrate to a topmost part of the second wire pattern,
wherein the third height is measured from the top surface of the substrate to a topmost part of the third wire pattern,
wherein a bottommost part of the third wire pattern is positioned at the second height and
wherein the second wire pattern is positioned between the first height and the second height.

10. The semiconductor device of claim 9 ,
wherein a bottommost part of the second wire pattern is positioned at the first height.

11. The semiconductor device of claim 8 , further comprising a fourth wire pattern, extending in the second direction, formed at a fourth height from the substrate of the second region,
wherein the fourth height is greater than the third height.

12. The semiconductor device of claim 11 ,
wherein the first wire pattern and the third wire pattern include a same material,
wherein the second wire pattern and the fourth wire pattern include a same material, and
wherein the first wire pattern and the second wire pattern include different materials.

13. The semiconductor device of claim 1 ,
wherein the first wire pattern and the second wire pattern include different materials.

14. The semiconductor device of claim 13 ,
wherein the first region is a PFET forming region and the second region is an NFET forming region, the first wire pattern includes at least one of SiGe and Ge, and
the second wire pattern includes at least one of Si and a III-V group compound semiconductor material.

15. The semiconductor device of claim 1 , further comprising
a dummy wire pattern interposed between the substrate of the second region and the second wire pattern and extended in the second direction,
wherein the dummy wire pattern is in contact with the substrate.

16. The semiconductor device of claim 1 ,
wherein the substrate includes an insulation layer,
wherein the first wire pattern and the second wire pattern are formed on the insulation layer.

17. The semiconductor device of claim 11 , further comprising:
a first source/drain including a first epitaxial layer and a second source/drain including a second epitaxial layer,
wherein the first source/drain is in contact with the first wire pattern and the third wire pattern, and
wherein the second source/drain is in contact with the second wire pattern and the fourth wire pattern.

18. The semiconductor device of claim 17 , wherein a portion of the first gate insulation layer is in contact with the first epitaxial layer of the first source/drain and a portion of the second gate insulation layer is in contact with the second epitaxial layer of the second source/drain.

19. The semiconductor device of claim 17 , further comprising a first seed layer and a second seed layer, wherein the first seed layer is interposed between the first epitaxial layer and the substrate of the first region, and wherein the second seed layer is interposed between the second epitaxial layer and the substrate of the second region.

20. The semiconductor device of claim 19 , wherein the first seed layer and the second seed layer include a same material.

21. A semiconductor device comprising:
a substrate including a first region and a second region;
a first wire pattern and a third wire pattern formed on the substrate of the first region;
a second wire pattern and a fourth wire pattern formed on the substrate of the second region;
a first gate electrode including a first portion and a second portion, wherein the first portion surrounds the first wire pattern and the third wire pattern;
a second gate electrode including a third portion and a fourth portion, wherein the third portion surrounds the second wire pattern and the fourth wire pattern;
a first gate spacer formed on the second portion of the first gate electrode;
a second gate spacer formed on the fourth portion of the second gate electrode;
a first source/drain being in contact with the first wire pattern and the third wire pattern;
a second source/drain being in contact with the second wire pattern and the fourth wire pattern;
a first gate insulation layer formed along a circumference of the first wire pattern, a circumfer

Assignees

• Suk Sung-Dae
• Seo Kang-Ill
• Samsung Electronics Co Ltd

Inventors

• Suk Sung-Dae
• Seo Kang-Ill

Classifications

• H10D84/8311

  the IGFETs characterised by having different channel structures · CPC title

• H01L21/823814

  Electricity · mapped topic

• H01L21/84

  Electricity · mapped topic

• H01L29/66742

  Electricity · mapped topic

• H01L21/823864

  Electricity · mapped topic