Phase error recovery circuitry and method for a magnetic recording device

Patent metadata

Field	Value
Publication number	US-9613652-B2
Application number	US-201514808721-A
Country	US
Kind code	B2
Filing date	Jul 24, 2015
Priority date	Jul 24, 2015
Publication date	Apr 4, 2017
Grant date	Apr 4, 2017

Abstract

A recording head is configured to write and read data sectors to and from a recording medium, such as a heat-assisted recording medium. A read channel is coupled to the recording head. Phase-locked loop (PLL) circuitry of the read channel is configured to detect a change in a phase error at a location of the data sector. The phase error change may be indicative of a mode-hop that occurred while writing the data sector to the medium. The PLL circuitry is configured to determine a phase offset using the phase error. A controller is configured to effect re-reading of the data sector location using the phase offset to recover the data sector location.

First claim

What is claimed is:

1. A method, comprising:
reading a data sector from a magnetic recording medium;
detecting a change in a phase error at a location of the data sector;
determining a phase offset using the phase error change; and
re-reading the data sector location using the phase offset to recover the data sector location.

2. The method of claim 1 , wherein:
the change in the phase error signal is indicative of a mode hop that occurred while writing the data sector to the medium; and
re-reading comprises re-reading the data sector location using the phase offset to recover the data sector location due to the mode hop.

3. The method of claim 1 , wherein detecting the change in the phase error comprises comparing the phase error to a threshold.

4. The method of claim 1 , wherein determining the phase offset comprises determining a magnitude and a direction of the change in the phase error.

5. The method of claim 1 , further comprising:
determining the location of the data sector where the phase error changed; and
re-reading the data sector location after injecting the phase offset at a start of the data sector location.

6. The method of claim 1 , wherein:
detecting the phase error change and determining the phase offset are performed by a phase-locked loop (PLL); and
the method further comprises increasing a bandwidth of the PLL in response to detecting the phase error change.

7. The method of claim 6 , wherein increasing a bandwidth of the PLL comprises increasing a phase coefficient of the PLL.

8. The method of claim 1 , wherein the method is performed in an error recovery mode.

9. An apparatus, comprising:
a phase detector of a read channel configured to receive an error signal for a data sector read from a magnetic recording medium, the phase detector configured to detect a change in a phase error in the error signal and to produce a phase error signal indicative of the phase error change;
a phase-locked loop (PLL) filter configured to receive the phase error signal and produce a phase signal;
a phase offset generator configured to receive the phase error signal and produce a phase offset signal using the phase error signal; and
an adder configured to sum the phase signal and the phase offset signal to produce a phase adjustment signal;
wherein the PLL filter has a bandwidth and is configured to increase the bandwidth in response to the phase error signal indicative of a mode hop that occurred while writing the data sector to the medium.

10. The apparatus of claim 9 , wherein:
the read channel comprises an analog-to-digital converter (ADC) having an input for receiving a read signal for the data sector and an output coupled to the phase detector; and
a clock generator having an input coupled to the adder and an output coupled to the ADC, the clock generator configured to generate an adjusted clock signal in response to the phase adjustment signal.

11. The apparatus of claim 9 , further comprising a threshold comparator coupled between the phase detector and the phase offset generator, the threshold comparator configured to compare the phase error signal to a threshold.

12. The apparatus of claim 9 , wherein the phase offset generator is configured to determine a magnitude and a direction of the change in the phase error.

13. The apparatus of claim 9 , wherein the phase offset generator is configured to determine a location of the data sector where the phase error changed.

14. An apparatus, comprising:
a recording head configured to write and read data sectors to and from a magnetic recording medium;
a read channel coupled to the recording head;
phase-locked loop (PLL) circuitry of the read channel configured to detect a change in a phase error at a location of the data sector, the PLL circuitry configured to determine a phase offset using the phase error; and
a controller configured to effect re-reading of the data sector location using the phase offset to recover the data sector location.

15. The apparatus of claim 14 , wherein the PLL circuitry comprises a PLL filter having a bandwidth, the PLL filter configured to increase the bandwidth in response to the phase error signal indicative of a mode hop that occurred while writing the data sector to the medium.

16. The apparatus of claim 14 , wherein the PLL circuitry is configured to inject the phase offset signal at a start of the data sector location during re-reading of the data sector.

17. The apparatus of claim 14 , wherein the PLL circuitry is configured to detect the change in the phase error by comparing the phase error to a threshold.

18. The apparatus of claim 14 , wherein the PLL circuitry is configured to determine a magnitude and a direction of the change in the phase error.

19. The apparatus of claim 14 , wherein the PLL circuitry is configured to determine the location of the data sector where the phase error changed.

Assignees

• Seagate Technology Llc

Inventors

• Link Michael J
• Buch Bruce Douglas
• Derras Belkacem

Classifications

• G11B2005/0021

  Thermally assisted recording using an auxiliary energy source for heating the recording layer locally to assist the magnetization reversal · CPC title

• G11B5/09

  Digital recording · CPC title

• G11B20/1024 Primary

  wherein a phase-locked loop [PLL] is used · CPC title

• G11B20/1816

  Testing · CPC title

• G11B2020/183

  wherein at least one additional attempt is made to read or write the data when a first attempt is unsuccessful · CPC title