Processing device for performing convolution operations

Patent metadata

Field	Value
Publication number	US-9613001-B2
Application number	US-201314136302-A
Country	US
Kind code	B2
Filing date	Dec 20, 2013
Priority date	Dec 20, 2013
Publication date	Apr 4, 2017
Grant date	Apr 4, 2017

Abstract

Systems and methods for performing convolution operations. An example processing system comprises: a processing core; and a convolver unit to apply a convolution filter to a plurality of input data elements represented by a two-dimensional array, the convolver unit comprising a plurality of multipliers coupled to two or more sets of latches, wherein each set of latches is to store a plurality of data elements of a respective one-dimensional section of the two-dimensional array.

First claim

What is claimed is:

1. A processing system, comprising:
a processing core; and
a convolver unit to apply a convolution filter to a plurality of input data elements represented by a two-dimensional array, the convolver unit comprising a plurality of multipliers coupled to two or more sets of latches, wherein each set of latches is to store a plurality of data elements of a respective one-dimensional section of the two-dimensional array;
wherein the convolution filter is provided by a rectangular matrix of pre-defined binary values, and wherein each set of latches comprises a number of latches which is equal to a dimension of the convolution filter.

2. The processing system of claim 1 , wherein the two or more sets of latches are provided by a first set of latches and a second set of latches, wherein the first set of latches is to store a first plurality of data elements of a first one-dimensional section of the two dimensional array and the second set of latches is to store a second plurality of data elements of a second one-dimensional section of the two-dimensional array.

3. The processing system of claim 1 , wherein the first one-dimensional section is provided by a first row the and second one-dimensional section is provided by a second row that is adjacent to the first row in the two-dimensional array.

4. The processing system of claim 1 , wherein each multiplier of the plurality of multipliers is to apply a convolution filter element to an input data element.

5. The processing system of claim 1 , wherein the convolver unit further comprises a subsampling circuit to perform at least one of: averaging a plurality of convolution results or determining a maximum value of convolution results.

6. The processing system of claim 1 , wherein the convolver unit further comprises a plurality of multiplexers, each multiplexer to select one of: a first latch output, a second latch output, or an external memory input to be supplied to a multiplier.

7. The processing system of claim 1 , wherein a latch of the first plurality of latches is connected in series with a latch of a second plurality of latches.

8. A method, comprising:
setting, by a processing device, an initial position of an input window in a two-dimensional array of input data elements;
applying a convolution filter to a plurality of input data elements referenced by the input window, wherein the convolution filter is provided by a rectangular matrix of pre-defined binary values, and wherein each set of latches comprises a number of latches which is equal to a dimension of the convolution filter;
shifting the input window, relatively to its previous position, by one or more positions along a one-dimensional section of the two-dimensional array; and
iteratively repeating the applying and shifting operations for a pre-defined number of times, wherein at least one of the applying operations comprises receiving an input data element from one of: an external memory or an internal latch of two or more sets of latches, each set of latches corresponding to a respective one-dimensional section of the two-dimensional array.

9. The method of claim 8 , wherein the applying and shifting operations comprise:
applying a convolution filter to a first plurality of input data elements referenced by the input window;
shifting the input window, relatively to its previous position, by one position along a first one-dimensional section of the two-dimensional array;
applying the convolution filter to a second plurality of input data elements referenced by the input window;
shifting the input window, relatively to the initial position, by one position along a second one-dimensional section of the two-dimensional array;
applying the convolution filter to a third plurality of input data elements referenced by the input window;
shifting the input window, relatively to its previous position, by one position along a first one-dimensional section of the two-dimensional array; and
applying the convolution filter to a fourth plurality of input data elements referenced by the input window.

10. The method of claim 9 , further comprising: repeating, a pre-defined number of times, at least one of sequences of the shifting and applying operations, wherein the number of times is determined as a pooling sample dimension reduced by one.

11. The method of claim 8 , wherein the first one-dimensional section is provided by a first row the and second one-dimensional section is provided by a second row that is adjacent to the first row in the two-dimensional array.

12. The method of claim 8 , further comprising:
performing a subsampling operation of convolution operation results.

13. The method of claim 8 , wherein the receiving further comprises storing the input data element in an internal latch.

14. A system-on-chip (SoC), comprising:
a plurality of convolver units, each convolver unit to apply a convolution filter to a plurality of input data elements represented by a two-dimensional array, each convolver unit comprising a plurality of multipliers coupled to two or more sets of latches, wherein each set of latches is to store a plurality of data elements of a respective one-dimensional section of the two-dimensional array;
wherein each convolver unit further comprises a plurality of multiplexers, each multiplexer to select one of: a first latch output, a second latch output, or an external memory input to be supplied to a multiplier of the plurality of multipliers.

15. The SoC of claim 14 , wherein the two or more sets of latches are provided by a first set of latches and a second set of latches, wherein the first set of latches is to store a first plurality of data elements of a first one-dimensional section of the two-dimensional array and the second set of latches is to store a second plurality of data elements of a second one dimensional section of the two-dimensional array.

16. The SoC of claim 14 , wherein the first one-dimensional section is provided by a first row the and second one-dimensional section is provided by a second row that is adjacent to the first row in the two-dimensional array.

17. The SoC of claim 14 , wherein each multiplier is to apply a convolution filter element to an input data element.

18. The SoC of claim 14 , further comprising a subsampling circuit to perform at least one of: averaging a plurality of convolution results or determining a maximum value of convolution results.

Assignees

• Intel Corp

Inventors

• Herrero Abellanas Enric
• Lupon Marc
• Falcon Ayose J
• Pratas Frederico C
• Latorre Fernando
• Lopez Pedro

Classifications

• G06F17/15

  Correlation function computation {including computation of convolution operations (arithmetic circuits for sum of products per se, e.g. multiply-accumulators G06F7/5443; digital filters, e.g. FIR, IIR, adaptive filters H03H17/00)} · CPC title

• G06V10/82 Primary

  using neural networks · CPC title

• G06V10/764

  using classification, e.g. of video objects · CPC title

• G06F18/2413

  based on distances to training or reference patterns · CPC title

• G06N3/045

  Combinations of networks · CPC title