Computer system and routing control method

US9612989B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9612989-B2
Application numberUS-201013997539-A
CountryUS
Kind codeB2
Filing dateDec 24, 2010
Priority dateDec 24, 2010
Publication dateApr 4, 2017
Grant dateApr 4, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The present invention eliminates the shortage of bus numbers in routing control using PCIe switches. A system port address (SPA) is associated with a destination bus number and is assigned to a port (external port) connected to a server and a device. When packets sent from the server or the device are received at the external port, the system port address (SPA) corresponding to the destination bus number having the packets is determined, and the SPA is added to the packets as a label. This SPA is used to route the packets sent between ports (internal ports) that connect switches. When the packets arrive at the external port to which the target server or device is connected, the destination bus number having packets is used to send the packets to the server or device connected to the external port.

First claim

Opening claim text (preview).

The invention claimed is: 1. A computer system in which a server and one or more devices are connected to each other by a plurality of PCIe switches each having a plurality of ports, the computer system sending packets between the server and the one or more devices through the plurality of ports of the plurality of PCIe switches, the plurality of ports include internal ports connecting the plurality of PCIe switches, an external port connected to the server, and an external port connected to one of the one or more devices, the external ports each including: a storage unit configured to store a system port address (SPA) in the computer system, the SPA being uniquely assigned to the external port; a conversion component configured to manage an association between a destination bus number and the SPA; and a SPA set setting component configured to set a set of SPAs, the internal ports each include a storage unit in which the SPA is not held, and a SPA set setting component configured to set the set of SPAs, wherein, when a port receives a packet holding at least a destination bus number from outside of the plurality of PCIe switches: if the packet receiving port is an external port, the packet receiving port's PCIe switch refers to the packet receiving port's conversion component and obtains the SPA associated with the destination bus number held by the packet, adds the obtained SPA to the packet, and sends the packet to a destination port included in the destination of the SPA using the SPA added to the packet to determine the set of SPAs specified by the packet receiving port's SPA set setting component, and if the packet receiving port is an internal port, the packet receiving port's PCIe switch sends the packet to the destination port included in the destination of the SPA by using the SPA added to the packet to determine the set of SPAs specified by the SPA set setting component, wherein, when the packet receiving port receives the packet from inside of the one of the plurality of PCIe switches: if the packet receiving port is an external port, the packet receiving port's PCIe switch removes the SPA added to the packet, and sends the packet to the server or one of the one or more devices connected to the packet receiving external port, based on the destination bus number held by the packet, and if the packet receiving port is an internal port, the packet receiving port's PCIe switch sends the packet to an internal port of another one of the plurality of PCIe switches connected to the packet receiving internal port. 2. The computer system according to claim 1 , wherein the set of SPAs specified by the SPA set setting component is in a range of SPAs to be destinations of packets that can pass through the packet receiving external port from inside of its PCIe switch to outside of its PCIe switch, and wherein one or more of the plurality of ports is identified as an the external port using a register for storing the SPA indicating the external port. 3. The computer system according to claim 1 , wherein contents of the conversion components, the SPA set setting components, and the registers for storing the SPAs are set in an initial setting by a management system connected by the plurality of PCIe switches. 4. The computer system according to claim 1 , wherein, a port (first port) of one switch (first switch) is connected to a port (second port) of another switch (second switch), wherein when a switch other than the first switch is connected to the second switch, the set of SPAs is set to the SPA set setting component of the first port, to include the SPA of the ports of the second switch and a next switch, wherein when a switch other than the first switch is not connected to the second switch, the set of SPAs is set to the SPA set setting component of the first port, to include the SPA of the port of the second switch, and wherein when a packet with a destination SPA included in the set of SPAs set by the SPA set setting component of the first port is input to the first switch, the first switch sends the packet with the destination SPA to the second switch by allowing the packet with the destination SPA to pass through the first port and then through the second port. 5. The computer system according to claim 1 , wherein the computer system includes a plurality of servers, wherein an accessible set including a plurality of external ports is defined within the computer system for each server. 6. The computer system according to claim 5 , wherein the plurality of external ports is included in a plurality of accessible sets, so that a device connected to one of the external ports transmits and receives the packet to and from the plurality of servers. 7. The computer system according to claim 1 , wherein the SPA and the destination bus number are represented in binary numbers, and wherein the binary number representing the SPA is set higher than the binary number of the bits representing the destination bus number, enabling connection of a larger number of devices and a larger number of servers as a single computer system. 8. The computer system according to claim 1 , wherein, for each port of the plurality of ports, whether the port is the external port or the internal port is determined by referring to the storage unit of the port, and wherein the port is the external port when the SPA is stored in the port, and the port is the internal port when the SPA is not stored in the port. 9. The computer system according to claim 1 , wherein the SPA set setting component is a set of SPAs used for determining the one or more of the plurality of ports to which the packet with the SPA is to be sent. 10. A packet routing control method in a computer system for sending packets between a server and one or more devices by a plurality of PCIe switches each having a plurality of ports, wherein the plurality of the ports include internal ports connecting the plurality of PCIe switches to each other, an external port connected to the server, and an external port connected to one of the one or more devices, the external ports each including: a storage unit configured to store a system port address (SPA) in the computer system, the SPA being uniquely assigned to the external port; a conversion component configured to manage an association between a destination bus number and the SPA; and a SPA set setting component configured to set a set of SPAs, the internal ports each include a storage unit in which the SPA is not held, and a SPA set setting component configured to set the set of SPAs, the method comprising: a port receiving a packet holding at least a destination bus number from outside the packet receiving port's PCIe switch: if the packet receiving port is an external port, the packet receiving port's PCIe switch refering to the packet receiving port's conversion component and obtaining the SPA associated with the destination bus number held by the packet, adding the obtained SPA to the packet, and sending the packet to a destination port included in the destination of the SPA using the SPA added to the packet to determine the set of SPAs specified by the packet receiving port's SPA set setting component, or if the packet receiving port is an internal port, the packet receiving port's PCIe switch sending the packet to the destination port included in the destination of the SPA by using the SPA added to the packet to determine the set of SPAs specified by the SPA set setting component, and the packet receiving port receiving a packet from inside the packet receiving port's PCIe switch, if the packet receiving port is an external port, the packet receiving port's PCIe switch removing the SPA ad

Assignees

Inventors

Classifications

  • for access to common bus or bus system · CPC title

  • using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title

  • Peripheral units, e.g. input or output ports · CPC title

Patent family

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Frequently asked questions

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What does patent US9612989B2 cover?
The present invention eliminates the shortage of bus numbers in routing control using PCIe switches. A system port address (SPA) is associated with a destination bus number and is assigned to a port (external port) connected to a server and a device. When packets sent from the server or the device are received at the external port, the system port address (SPA) corresponding to the destination …
Who is the assignee on this patent?
EGUCHI Shuhei, Yamagata Ryo, Todaka Takashi, and 1 more
What technology area does this patent fall under?
Primary CPC classification G06F13/4022. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Apr 04 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).