Multi-tiered caching for data storage management in a device

Patent metadata

Field	Value
Publication number	US-9612956-B2
Application number	US-201414575616-A
Country	US
Kind code	B2
Filing date	Dec 18, 2014
Priority date	Mar 15, 2013
Publication date	Apr 4, 2017
Grant date	Apr 4, 2017

Abstract

A data storage device includes one or more storage media that include multiple physical storage locations. The device also includes at least one cache memory having a logical space that includes a plurality of separately managed logical block address (LBA) ranges. Additionally, a controller is included in the device. The controller is configured to receive data extents addressed by a first LBA and a logical block count. The controller is also configured to identify at least one separately managed LBA range of the plurality of separately managed LBA ranges in the at least one cache memory based on LBAs associated with at least some of the received data extents. The controller stores the at least some of the received data extents in substantially monotonically increasing LBA order in at least one physical storage location, of the at least one cache memory, assigned to the identified at least one LBA range.

First claim

What is claimed is:

1. A method comprising:
providing, in a data storage device, one or more storage media that comprise a plurality of physical storage locations, wherein the plurality of physical storage locations includes a plurality of pages of a solid state memory and a pool of shingled disc bands;
providing, in the data storage device, a plurality of cache memory levels comprising:
a first level cache memory comprising the plurality of pages; and
a second level cache memory having a logical space that includes a plurality of separately managed logical block address (LBA) ranges;

storing data extents addressed by a first LBA and a logical block count into the first level cache memory substantially in an order in which the data extents are received in the data storage device;
gathering at least some of the data extents stored in the first level cache memory;
dynamically assigning one or more shingled disc bands of the pool of shingled disc bands to one or more separately managed LBA ranges of the plurality of separately managed LBA ranges of the second level cache memory;
identifying at least one LBA range of the plurality of LBA ranges in the second level cache memory based on LBAs associated with the gathered data extents;
dynamically assigning at least one available shingled disc band from any singled disc bands, of the pool of shingled disc bands, assigned to the identified LBA range of the second level cache memory; and
storing the gathered data extents in substantially monotonically increasing LBA order in the at least one available shingled disc band assigned to the identified at least one LBA range of the second level cache memory.

2. The method of claim 1 and further comprising transferring at least some of the data extents in the at least one available shingled disc band assigned to the identified at least one LBA range of the second level cache memory to at least one of the plurality of physical storage locations, on the one or more storage media, assigned to a main storage physical space.

3. The method of claim 1 and wherein the solid state memory comprises a plurality of erasure blocks, with each different one of the plurality of erasure blocks comprising one or more different ones of the plurality of pages.

4. The method of claim 1 and wherein the one or more storage media comprise a homogeneous memory portion, and wherein the homogenous memory portion comprises a first area that serves as the second level cache memory and a second area that serves as a main storage physical space.

5. The method of claim 1 and further comprising:
providing a main storage logical space comprising a plurality of logical elements; and
dynamically assigning different ones of the plurality of physical storage locations of the one or more storage media to different ones of the plurality of logical elements.

Assignees

• Seagate Technology Llc

Inventors

• Feldman Timothy R
• Kowles Andrew M
• Gaertner Mark Allen
• Edgar Brian T

Classifications

• G06F12/0811 Primary

  with multilevel cache hierarchies · CPC title

• G11C2207/2245

  Memory devices with an internal cache buffer · CPC title

• G06F2212/608

  Details relating to cache mapping · CPC title

• G11B20/10527 Primary

  Audio or video recording; Data buffering arrangements (G11B20/12 - G11B20/18 take precedence) · CPC title

• G11C7/1012

  Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating · CPC title