System constraints-aware scheduler for heterogeneous computing architecture

Patent metadata

Field	Value
Publication number	US-9612879-B2
Application number	US-201314106022-A
Country	US
Kind code	B2
Filing date	Dec 13, 2013
Priority date	Aug 1, 2013
Publication date	Apr 4, 2017
Grant date	Apr 4, 2017

Abstract

Processors, systems, and methods are arranged to schedule tasks on heterogeneous processor cores. For example, a scheduler is arranged to perform a heuristics based function for allocating operating system tasks to the processor cores. The system includes a hint generator providing a system constraints-aware function that biases the scheduler to select a processor core depending on the change in one or more performance constraint parameters.

First claim

What is claimed is:

1. A processor comprising:
a plurality of processor cores, each of which is arranged to perform processing tasks, and wherein at least one of the processor cores is of a different architecture than the other core(s);
a scheduler that is arranged to receive task identifiers of respective processing tasks from a task queue and to allocate a selected core of the processor cores for each respective processing task received from the task queue; and
a hint generator that is arranged to monitor performance constraint parameters of the processor during operation of the processor and to generate a hint in response to the monitored performance parameters, wherein the scheduler is arranged to allocate the respective processing task from the task queue to the selected core in response to the generated hint, wherein the generated hint is generated in response to a bias threshold determined in response to a first comparison of a first monitored performance constraint parameter with a first system constraint setting and to a second comparison of a second monitored performance constraint parameter with a second system constraint setting, wherein the selected core is arranged to execute the respective processing task from the task queue, wherein the hint generator is arranged to store the first and the second system constraint settings, and wherein the bias threshold is determined using a weighting factor for each of the first and second system constraint settings.

2. The processor of claim 1 , wherein at least one of the weighting factors is dynamically adjusted in response to a change in at least one of the monitored performance parameters.

3. The processor of claim 1 , wherein the bias threshold is determined in response determining the greater of respective thresholds of the first and second system constraint settings.

4. The processor of claim 3 , wherein the bias threshold reflects a bias towards a core type that is associated with the lesser of respective thresholds of the first and second system constraint settings.

5. The processor of claim 4 , comprising a heterogeneous multicore scheduler that is arranged to receive the bias threshold and to allocate the selected core of the processor cores in accordance with the bias reflected towards the core type that is associated with the greater of respective thresholds of the first and second system constraint settings.

6. The processor of claim 1 , wherein one of the performance constraint parameters includes a user defined mode, wherein each user mode is associated with a threshold value.

7. The processor of claim 1 , wherein the first system constraint setting is a performance constraint parameter of a type that includes temperature constraints.

8. The processor of claim 7 , wherein the second system constraint setting is a performance constraint parameter of a type that includes user mode constraints or power constraints.

9. The processor of claim 1 , wherein the plurality of processor cores includes a first core type that consumes more power than a second core type.

10. A processor, comprising:
a plurality of processor cores, each of which is arranged to perform processing tasks, and wherein at least one of the processor cores is of a different architecture than the other core(s);
a scheduler that is arranged to receive task identifiers of respective processing tasks from a task queue and to allocate a selected core of the processor cores for each respective processing task received from the task queue; and
a hint generator that is arranged to monitor performance constraint parameters of the processor during operation of the processor and to generate a hint in response to the monitored performance parameters, wherein the scheduler is arranged to allocate the respective processing task from the task queue to the selected core in response to the generated hint, wherein the generated hint is generated in response to a bias threshold determined in response to a first comparison of a first monitored performance constraint parameter with a first system constraint setting and to a second comparison of a second monitored performance constraint parameter with a second system constraint setting, and wherein the first monitored performance constraint parameter is of a constraint type that is different from the constraint type of the second monitored performance constraint parameter, wherein one of the performance constraint parameters includes a user defined mode, wherein each user mode is associated with a threshold value, and wherein the bias threshold is determined using a weighting factor for each of the first and second system constraint settings.

11. The processor of claim 10 , wherein the selected core is arranged to execute the respective processing task from the task queue.

12. The processor of claim 11 , wherein the hint generator is arranged to select the first and the second system constraint settings in response to the respective task identifier.

13. The processor of claim 10 , wherein the hint generator is arranged to store the first and the second system constraint settings.

14. A scheduling system, comprising:
a scheduler that is communicatively coupled with a plurality of heterogeneous processor cores and with a task queue including one or more processing tasks, and wherein the scheduler is arranged to allocate the processing task from the task queue to a selected processor core of the plurality of processor cores based on a heuristic function and a load balancing mechanism; and
a hint generator that is arranged to monitor predetermined performance constraint parameters of the processor during operation of the scheduler and to generate a hint for biasing a selection of a core type of the plurality of heterogeneous processor cores in response to the monitored performance parameters, wherein the generated hint is arranged to bias a selection of a core type of the plurality of heterogeneous processor cores, and wherein the scheduler is arranged to allocate the selected core of the processor cores in accordance with the generated hint, wherein the generated hint is generated in response to a bias threshold determined in response to a first comparison of a first monitored performance constraint parameter with a first system constraint setting and to a second comparison of a second monitored performance constraint parameter with a second system constraint setting, wherein the system constraints are limits of performance constraint parameters inside which the processor is to operate, and wherein the first monitored performance constraint parameter is of a constraint type that is different from the constraint type of the second monitored performance constraint parameter, and wherein the bias threshold is determined using a weighting factor for each of the first and second system constraint settings.

15. The system of claim 14 , wherein the hint is a bias threshold generated in response to comparing each of the monitored performance constraint parameters with one or more related system constraints each of which is associated with a respective core type.

16. The system of claim 15 , wherein the scheduler allocates processing tasks in accordance with the bias threshold when the bias threshold exceeds a predefined threshold value, and wherein each monitored performance constraint parameter includes at least two of a temperature, a user defined mode, and a battery level of a computing device.

17. A method, comprising:
receiving from a task queue a succession of processing tasks for execution upon a plurality of heterogeneous processor c

Assignees

• Texas Instruments Inc
• Texas Instruments Inc

Inventors

• Matthes Katrin
• Ramonda Damien

Classifications

• G06F9/5094 Primary

  where the allocation takes into account power or heat criteria (power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206) · CPC title

• Y02B60/142

  Cross-Sectional Technologies · mapped topic

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title