Hardware device for accelerating the execution of a systemC simulation in a dynamic manner during the simulation

Patent metadata

Field	Value
Publication number	US-9612863-B2
Application number	US-201213984525-A
Country	US
Kind code	B2
Filing date	Feb 13, 2012
Priority date	Feb 15, 2011
Publication date	Apr 4, 2017
Grant date	Apr 4, 2017

Abstract

A device is provided for accelerating, on a platform comprising a plurality of processing units, the execution of a SystemC simulation of a system, said simulation comprising a SystemC kernel and SystemC processes. The device comprises hardware means for scheduling the SystemC processes on the processing units in a dynamic manner during the execution of the simulation, these means making it possible notably to preempt the processing units.

First claim

The invention claimed is:

1. A hardware device for accelerating an execution of a SystemC simulation of a system on a platform, said SystemC simulation comprising a SystemC kernel and SystemC processes, said platform comprising a plurality of processing units for executing SystemC processes, the device comprising a hardware control unit for executing the SystemC kernel, the SystemC kernel being configured to schedule the SystemC processes in parallel on the plurality of processing units in a dynamic manner during the execution of the simulation,
wherein the SystemC kernel is configured to schedule the SystemC processes on the processing units in parallel, and the hardware control unit for executing the SystemC kernel is configured to preempt the SystemC processes, a processing unit being preempted if a first SystemC process executed by said processing unit is an idle process on standby awaiting a synchronization with a second SystemC process, said processing unit saving its execution context in a memory shared by the plurality of processing units and beginning an execution of another SystemC process, the execution of said first SystemC process being resumed subsequently on a processing unit,
wherein the hardware control unit for executing the SystemC kernel scheduling the SystemC processes includes:
a SystemC kernel evaluation module for executing a code of the SystemC kernel;
an event tag unit for managing events, the event tag unit including a list of all generatable events associated with identifiers of the SystemC processes sensitive to said generatable events, and
a watchdog time unit for managing synchronization times of the SystemC processes the watchdog time unit including a watchdog for each of the SystemC processes.

2. The hardware device as claimed in claim 1 , wherein the simulated system is described at a Register Transfer Level (RTL) level or at a Transactional Level Modeling (TLM) level.

3. The hardware device as claimed in claim 1 , wherein the SystemC kernel evaluation module includes a Reduced Instruction Set Computing (RISC) processor for executing instructions forming the SystemC kernel.

4. The hardware device as claimed in claim 1 , wherein the SystemC kernel evaluation module includes a graph of a dependency between the SystemC processes to activate child processes, provided that respective parent processes of said child processes have been executed.

5. The hardware device as claimed in claim 1 , wherein the watchdog time unit includes:
a counter providing a current simulated time;
a first memory containing a list of the simulated times to be reached by each of the SystemC processes currently executing on the plurality of processing units;
a second memory containing a list of states of each of the SystemC processes currently executing on the plurality of processing units, a state in the list indicating that the SystemC process is in an active state or in a standby state;
at least one comparator for comparing a current simulated time with simulated times to be reached by each of the SystemC processes;
the state of the SystemC process switching from the active state to the standby state provided that the current simulated time has reached the simulated time to be reached associated with said SystemC process.

6. The hardware device as claimed in claim 1 , wherein the event tag unit includes:
a first memory containing a list of event identifiers;
a second memory containing, for each event identifier, an address of a list of processes sensitive to an event respectively associated with each said event identifier, said address being a pointer to a third memory comprising said list of processes.

Assignees

• Ventroux Nicolas
• Commissariat Energie Atomique

Inventors

• Ventroux Nicolas

Classifications

• G06F30/33

  Design verification, e.g. functional simulation or model checking · CPC title

• G06F9/4887

  involving deadlines, e.g. rate based, periodic · CPC title

• G06F30/20

  Design optimisation, verification or simulation (optimisation, verification or simulation of circuit designs G06F30/30) · CPC title

• G06F30/331

  with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation · CPC title

• G06F9/4881 Primary

  Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues · CPC title