Apparatus and methods to control power on PCIe direct attached nonvolatile memory storage subsystems

Patent metadata

Field	Value
Publication number	US-9612763-B2
Application number	US-201414493567-A
Country	US
Kind code	B2
Filing date	Sep 23, 2014
Priority date	Sep 23, 2014
Publication date	Apr 4, 2017
Grant date	Apr 4, 2017

Abstract

Techniques for controlling power on a PCIe direct attached non-volatile memory storage system are disclosed. In one particular embodiment, the techniques may be realized as a method for controlling power including providing power to a memory attached via the PCIe interface; monitoring a state of the attached memory; determining whether a new operation to be implemented on the attached memory would cause the power provided to the memory to exceed a preset threshold; and stalling execution of the new operation on the attached memory when it is determined that the new operation would exceed the preset threshold while continuing execution of preexisting operations on the attached memory.

First claim

What is claimed is:

1. A method for controlling power on a Peripheral Component Interconnect Express (PCIe) interface, comprising:
providing power to a memory attached via the PCie interface;
monitoring a state of the attached memory;
determining whether a new operation to be implemented on the attached memory would cause the power provided to the memory to exceed a preset threshold;
stalling execution of the new operation on the attached memory when it is determined that the new operation would exceed the preset threshold while continuing execution of preexisting operations on the attached memory;
monitoring power consumption of the attached memory while idle;
monitoring power consumption of the attached memory while executing at least one predetermined operation; and
determining a power credit for each operation based on a comparison of the monitored power consumption while idle and while executing the at least predetermined operation.

2. The method of claim 1 , wherein the attached memory is a directly attached non-volatile memory storage system.

3. The method of claim 2 , wherein the non-volatile memory storage system is a solid state drive.

4. The method of claim 3 , wherein the solid state drive is flash memory comprising stacks of die, and wherein the monitoring comprises determining how many die are simultaneously executing operations.

5. The method of claim 4 , wherein the preset threshold is a predetermined number of die actively executing operations simultaneously.

6. The method of claim 1 , further comprising:
executing the operation when it is determined that the new operation would not exceed the preset threshold.

7. The method of claim 1 , further comprising:
applying a timing offset to the new operation.

8. The method of claim 7 , further comprising:
monitoring power consumption of the attached memory.

9. The method of claim 8 , further comprising:
changing the timing offset based on monitored power consumption.

10. The method of claim 8 , further comprising:
generating an alert based on the monitored power consumption of the attached memory.

11. The method of claim 8 , further comprising:
determining whether the monitored power consumption of the attached memory has exceeded a predetermined power threshold for predetermined time period; and
controlling an I/O rate of the attached memory based on the determination.

12. The method of claim 11 , wherein the I/O rate of the attached memory is decreased when it is determined that the monitored power consumption of the attached memory has exceeded the predetermined power threshold for the predetermined time period.

13. The method of claim 11 , wherein the I/O rate of the attached memory is maintained when it is determined that the monitored power consumption of the attached memory has not exceeded the predetermined power threshold for the predetermined time period.

14. The method of claim 1 , wherein the power is provided directly to the memory via a plurality of PCIe interface channels.

15. The method of claim 1 , wherein the predetermined operation is one of a read, a write, and an erase operation.

16. The method of claim 1 , further comprising:
assigning a total number of system credits for the attached memory; assigning at least one credit to the new operation;
determining whether the assigned at least one credit of the new operation exceeds the total number of system credits; and
executing the new operation based on the determination of whether the assigned at least one credit would exceed the total number of system credits.

17. The method of claim 16 , wherein execution of the new operation is stalled until the assigned credit would no longer exceed the total number of system credits.

18. A computer program product comprising a series of instructions stored on one or more non-transitory processor readable storage media, which when executed by a processor, perform a process for controlling power on a Peripheral Component Interconnect Express (PCie) interface; the instructions including:
providing power to a memory attached via the PCie interface;
monitoring a state of the attached memory;
determining whether a new operation to be implemented on the attached memory would cause the power provided to the memory to exceed a preset threshold;
stalling execution of the new operation on the attached memory when it is determined that the new operation would exceed the preset threshold while continuing execution of preexisting operations on the attached memory;
monitoring power consumption of the attached memory while idle;
monitoring power consumption of the attached memory while executing at least one predetermined operation; and
determining a power credit for each operation based on a comparison of the monitored power consumption while idle and while executing the at least one predetermined operation.

19. A system for controlling power on a Peripheral Component Interconnect Express (PCie) interface, the system comprising:
a storage media storing instructions; and
a processor configured to execute the instructions to:
supply power to a memory attached via the PCie interface;
monitor a state of the attached memory;
determine whether a new operation to be implemented on the attached memory would cause the power provided to the memory to exceed a preset threshold;
stall execution of the new operation on the attached memory when it is determined that the new operation would exceed the preset threshold while continuing execution of preexisting operations on the attached memory;
monitor power consumption of the attached memory while idle;
monitor power consumption of the attached memory while executing at least one predetermined operation; and
determine a power credit for each operation based on a comparison of the monitored power consumption while idle and while executing that at least one predetermined operation.

Assignees

• HGST Netherlands BV
• Western Digital Tech Inc

Inventors

• Skandakumaran Krishanth
• Medapati Arun Kumar
• Namala Sri Rama
• Narasimha Ashwin
• Kumar B Ajith

Classifications

• G06F11/3037 Primary

  where the computing system component is a memory, e.g. virtual memory, cache (accessing, addressing or allocating within memory systems or architectures G06F12/00; checking stores for correct operation G11C29/00) · CPC title

• G06F1/3225

  of memory devices · CPC title

• G06F1/3253

  Power saving in bus · CPC title

• G06F3/0625 Primary

  Power saving in storage systems · CPC title

• G06F1/329

  by task scheduling · CPC title